Figure 4-1. Mvme5100 Block Diagram - Motorola AltiVec MVME5100 Series Installation & Use Manual

Functional Description
4
4-4
The following diagram illustrates the architecture of the MVME5100
Single Board Computer.
L2 Cache
1M,2M
Processor
750 Max
Clock
System Memory Controller (SMC)
Generator
33MHz 32/64-bit PCI Local Bus
TL16C550
UART
Ethernet 1
10/100TX
VME P2

Figure 4-1. MVME5100 Block Diagram

Mezzanine SDRAM
32MB to 512MB
SDRAM
32MB to 512MB
Hawk Asic
and PCI Host Bridge (PHB)
Hawk X-bus
VME Bridge
Ethernet 2
Universe 2
10/100TX
Buffers
HDR
761 or PMC
VME P1
Computer Group Literature Center Web Site
System
Registers
TL16C550
UART/9pin
planar
FLASH
1MB to 17MB
RTC/NVRAM/WD
M48T37V