HP PageWriter XL M1705B Service Manual page 215

nADS
nBHE
nBLE
nLOCK
nPVENd
nRD
nRDY
nWAIT
nWEH
nWEL
OBITl
PCLK
TURBO
VBACK7
VIN
WRn
CPU address strobe-active low.
CPU byte high enable strobe.
CPU byte low enable strobe.
CPU lock-active low.
Preview enable. Asserted low during select of
preview I/O or memory.
Read enable signal for EPROM.
Ready. Derived from wait state generator.
Terminates current bus cycle.
Wait states are forced into the bus cycle as long as
nWAIT is asserted.
High byte write enable.
Low byte write enable.
General purpose output bit.
Phase-synchronized reference signal that indicates
the CPU bus cycle phase. 0 = phase 1, 1 = phase 2.
Changes the speed of the system clock. 1 = 32 MHz,
0 = 8 MHz.
Backup 5 volts for DRAM.
Rectified AC-ranges from 15 to 31 volts depending
on line voltage and load.
Write/Read. CPU control bus signal. Distinguishes
write cycles from read cycles.
Table A-9. Disk Power Connector J14
Connector Pin Assignments A-9