Kauai Labs navX-MXP User Manual page 87

Advanced
Register Protocol
When accessing the navX-MXP via the SPI bus, this following pattern is used:
– When the SPI bus master is not communicating with the navX-MXP, the SPI bus master must
hold the chip select (CS) line high.
– The SPI bus master lowers the CS line.
– The SPI bus master next transmits the register address it intends to read from or write to. If
writing, the upper bit (0x80) must be set; if this upper bit is clear, this indicates a read
transaction.
– If the SPI bus master is reading, it next transmits the count of registers it wishes to read from.
This count must be at least 1, and must be not exceed the maximum register address less the
requested register address.
– If the SPI bus master is writing, it transmits the register value to be written to the specified
register address.
– The SPI bus master finally transmits an 8-bit CRC (see CRC calculation section below) which
is calculated on the register address and count values previously transmitted.
– If the SPI bus master is writing, it raises the CS line to complete the write sequence.
– If the SPI bus master is reading:
– The SPI bus master raises the CS line.
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