Kauai Labs navX-MXP User Manual page 86

Advanced
Register Protocol
on both the I2C and SPI bus.
Register-based protocol overview
Unlike the streaming Serial protocol, which periodically sends out updates messages whenever
new data is available, the register based protocol is a "polled" interface, in that the consumer of
the navX-MXP data (in this case referred to as a "bus master") can request data from the navX-
MXP at any time. At the same time, when using the register-based protocol the bus master does
not know when new data is available.
To help this situation, a timestamp – which is updated whenever new data is available – is made
available. Therefore, the general approach to ensure each new data sample is retrieved is to
regularly (at the navX-MXP update rate) retrieve both the timestamp and the data of interest),
and if the timestamp differs from the previous timestamp by the update rate as expressed in
milliseconds, then the data sample just retrieved is current, and no data has been missed.
I2C Overview
The navX-MXP responds to 7-bit address 50 (0x32) on the I2C bus. If accessing the navX-MXP
via the MXP I2C bus, ensure that no other device at that address is on the same bus.
The navX-MXP I2C bus operates at a speed up to 400Khz.
When accessing the navX-MXP via the I2C bus, this following pattern is used:
– The I2C bus master sends the navX-MXP I2C address. The highest bit is set to indicate the
bus master intends to write to the navX-MXP. If the highest bit is clear, this indicates the bus
master intends to read from the navX-MXP.
– The I2C bus master next sends the starting register address it intends to write to or read from.
– The I2C bus master next initiates I2C bus transactions. The navX-MXP supports I2C burst
mode for read operations, therefore the navX-MXP will respond with register values as long as
the I2C bus master continues the transaction, and as long as the last register address has not
yet been reached.
If instead the I2C bus master intends to write data to a writable navX-MXP register, the bus
master should transmit the new register value immediately after sending the register address.
SPI Overview
The navX-MXP SPI data is communicated as follows:
– Most-significant bit first – Maximum Bitrate: 2mbps – Clock Polarity/Clock Phase –
Mode 3
83