Table 1: Fpga Choices - Sundance Spas SMT398 User Manual

Version 1.1.1
This Xilinx Virtex II, is responsible for the provision of up to 4 SHBs, up to 6
ComPorts, the global bus and QDR/ZBT memory banks (In FULL configuration, see
0 Ordering information:)
Device Syste
m
gates
XC2V1000 1M
XC2V1500 1.5M
XC2V2000 2M
XC2V3000 3M
XC2V4000 4M
XC2V6000 6M
XC2V8000 8M

Table 1: FPGA Choices

The Xilinx FPGA is configured from one of several modes:
Slave SelectMAP.
JTAG/Boundary scan
And from one of several sources:
ComPort 3 (Using Slave SelectMAP)
Parallel cable III-IV (Using JTAG)
MultiLINX cable. (Using JTAG or Slave SelectMAP)
At power up the FPGA is not configured.
LED L5 (See Figure 10:SMT398 Components placement-Top
hand corner of the picture) will be lit upon FPGA configuration.
Page 16 of 38
CLB(1 CLB = 4 slices = Max 128
bits)
Array
Row x
Col
Slices
40x32 5,120
48x40 7,680
56x48 10,752
64x56 14,336
80x72 23,040
96x88 33,792
112x104 46,592
Maximum
distribute
Multiplie
d RAM
r
Kbits
blocks
160 40
240 48
336 56
448 96
720 120
1,056 144
1,456 168
SMT398 User Manual
SelectRAM Blocks
18-Kbit Max RAM
Block (Kbits)
40 720
48 864
56 1,008
96 1,728
120 2,160
144 2,592
168 3,024
view, bottom right
DCM
s
8
8
8
12
12
12
12