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Version 1.1.1
Page 21 of 38
SMT398 User Manual
ZBT3
ZBT4
4 independent Memory
banks with their own
address, data and control
signals.
ZBT1
Connections for 1
memory bank only are
CLK
ZBT2
shown here.
Clk Feedback
CLKZBT_FB
CLKZBT
16
21
1
ZxDATA[15:0]
1
1
ZxADDR[20:0]
2
1
ZxWEN
FPGA
1
ZxCE
ZxOE
ZxCS2/CS2n
ZxADV
ZxLBOn
Figure 6:SMT398 ZBT Memory Banks arrangement
QDR (Quad Data Rate)
Up to 8 Mbytes of
QDR
(Quad Data Rate) Synchronous Pipelined Burst SRAMs
memory is provided with direct access to the FPGA. (Provision has been made to
accommodate up to 64 Mbytes of QDR when the memory chips will be available)
The QDR operation is possible by supporting DDR (Double Data Rate) read and
writes operations through separate data output and input ports with the same cycle.
Memory bandwidth is maximized as data can be transferred into SRAM on every
rising edge of the write clock, and transferred out of SRAM on every rising edge of
the read clock. (Read clock is write clock shifted of 90 degrees)
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