Sundance Spas SMT398 User Manual
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Sundance Spas SMT398 User Manual

Sundance Spas SMT398 User Manual

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Summary of Contents for Sundance Spas SMT398

  • Page 1 SMT398 User Manual...

  • Page 2: Revision History

    Version 1.1.1 Page 2 of 38 SMT398 User Manual Revision History Date Comments Engineer Version 18.07.03 First released version 1.0.0 22.08.03 TIM CONFIG signal feature described 1.1.0 27.08.03 Minor corrections 1.1.1...

  • Page 3: Table Of Contents

    Related Documents ....................7 Block Diagram ......................7 Mechanical Interface: TIM Standard................8 SMT398 Installation....................8 SMT398 Alone ......................8 SMT398 + DSP TIM....................9 FPGA Configuration ....................10 Electrical Interface ....................10 The service CPLD ....................10 CPLD Functions ....................11 Virtex II Bitstream Format..................
  • Page 4 Version 1.1.1 Page 4 of 38 SMT398 User Manual SHB Inter Modules solutions ................25 SHB 16-bit Interface ..................25 Global bus......................26 Clocks ........................26 Power Supplies ..................... 27 DC/DC Converter ....................28 Linear Voltage regulator ..................28 Fan ........................28 Power Consumption....................

  • Page 5: Table Of Figures

    Figure 2: FPGA configuration in SelectMap mode using CPLD..........11 Figure 3: ComPort word Byte order..................12 Figure 4: V II Configuration Bitstream Word Format ..............15 Figure 5: JTAG Chain on the SMT398 ...................18 Figure 6:SMT398 ZBT Memory Banks arrangement .............21 Figure 7:SMT398 QDR Width expansion arrangement............22 Figure 8:SMT398 ComPorts connections ................23...

  • Page 6: Physical Properties

    Version 1.1.1 Page 6 of 38 SMT398 User Manual Physical Properties Dimensions See Physical specifications of TI TIM specification & user’s guide Weight Varies in function of board configuration Supply Voltages See Power Supplies Supply Current See Power Supplies...

  • Page 7: Introduction

    1.5V Core connector x4 1.5V/3.3V I/O 2,4,8 or 16Mbytes ZBT- 183 I/O pins; 16-bit data RAM as SMT358 4 LEDs or 4 I/O pins J2 Bottom Primary TIM J3 Global Expansion Connector Connector 4xComm-Port/SDL 1;2;4 & 5 Figure 1:SMT398 Block Diagram...

  • Page 8: Mechanical Interface: Tim Standard

    Sundance if your system architecture differs. SMT398 Alone You can fit the SMT398 on its own, on the first TIM site of one of Sundance’s 3.3v compatible carrier boards plugged in a host computer (PC, PCI, VME carrier etc…), like SMT310Q, SMT328, SMT300 etc…)

  • Page 9: Smt398 + Dsp Tim

    SMT398 User Manual SMT398 + DSP TIM You can fit the SMT398 coupled with a DSP module on any of Sundance carrier boards: Stand alones or plugged in a Host. The DSP module can then be used to provide the SMT398 FPGA configuration bistream and to communicate with the host.

  • Page 10: Fpga Configuration

    The service CPLD The CPLD allows for FPGA configuration in slave SelectMap mode. At power up or after a Reset of the SMT398, the CPLD is configured and implements a ComPort link receiver on ComPort 3. The CPLD is connected to ComPort number 3 of the SMT398 TIM connector.

  • Page 11: Cpld Functions

    Version 1.1.1 Page 11 of 38 SMT398 User Manual Figure 2: FPGA configuration in SelectMap mode using CPLD CPLD Functions • Decode Commands coming on ComPort 3. • To Implement a ComPort Receiver on ComPort 3 after Reset or at Power up.

  • Page 12: Figure 3: Comport Word Byte Order

    Version 1.1.1 Page 12 of 38 SMT398 User Manual Decode Commands At power up, after a TIM global Reset, or once the FPGA configuration process is over, the CPLD reads any word coming on its ComPort. If a received word cannot be recognized as a command, the word is read completely but ignored.
  • Page 13 Once the ENDKEY command is received, the CPLD releases ComPort 3. Reset Control TIM Global Reset The CPLD is connected to a TIM global Reset signal provided to the SMT398 via its TIM connector J4 pin 30. (See Figure 10:SMT398 Components placement-Top view).

  • Page 14: Virtex Ii Bitstream Format

    • The system needs to keep running and can’t be interrupted by a global Reset pulse when the FPGA needs to be configured with a new bitstream. Notes: • TIM CONFIG is only available on SMT398 v3. The SMT398 version is written on TOP of the board (See Figure 10:SMT398 Components placement-Top view).

  • Page 15: Bitstream Re-Formatting

    Version 1.1.1 Page 15 of 38 SMT398 User Manual Byte0 Byte1 Byte2 Byte3 24 23 16 15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31...

  • Page 16: Table 1: Fpga Choices

    Parallel cable III-IV (Using JTAG) MultiLINX cable. (Using JTAG or Slave SelectMAP) At power up the FPGA is not configured. LED L5 (See Figure 10:SMT398 Components placement-Top view, bottom right hand corner of the picture) will be lit upon FPGA configuration.

  • Page 17: Fpga In System Programming

    Virtex II is XC2V3000 or above and if your CPLD design version allows it. SMT398 Alone Host software can be developed to communicate with the SMT398. See SMT6025 User Manual on Sundance Web site for more information on how to develop Host applications for Sundance Hardware.

  • Page 18: Jtag/Boundary Scan

    The CPLD is pre-programmed by Sundance. Do NOT try to reprogram the CPLD without SUNDANCE approval Figure 5: JTAG Chain on the SMT398 When accessing the board using JTAG, the CPLD can be bypassed and you can configure the FPGA only.

  • Page 19: Configuring With Multilinx

    Sundance. Contrary to the original design, the CPLD is dedicated to control the FPGA and does not provide a communication channel to user logic residing on the FPGA anymore. The CPLD is connected to ComPort number 3 of the SMT398 connector, which cannot be used anymore by the FPGA to transfer data.

  • Page 20: Memory

    Version 1.1.1 Page 20 of 38 SMT398 User Manual Memory Pipelined ZBTRAM Up to 16Mbytes of pipeline ZBT memory is provided with direct access by the FPGA. The ZBTRAM is designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa.

  • Page 21: Qdr (Quad Data Rate)

    ZxOE ZxCS2/CS2n ZxADV ZxLBOn Figure 6:SMT398 ZBT Memory Banks arrangement QDR (Quad Data Rate) Up to 8 Mbytes of (Quad Data Rate) Synchronous Pipelined Burst SRAMs memory is provided with direct access to the FPGA. (Provision has been made to...

  • Page 22: Figure 7:Smt398 Qdr Width Expansion Arrangement

    The memory is expected to be clocked at 166 MHz allowing a data throughput rate of 1.3 GBytes/s. The memory bank of the SMT398 is composed of 2 devices added in parallel in width expansion architecture. The address bus, input clocks, R# and W# are common to both devices.

  • Page 23: Comports

    Comm-port 3 / Comm-port 0 FPGA Virtex-II FF896/ FF1152 Xilinx XC95288 CS280 XC2V1000 - CPLD on Comm-Port 23 I/O pins XC2V8000 #0 and #3 720 to 824 I/O Pins 1.5V Core 3.3V I/O J2 Bottom Primary TIM Connector 4xComm-Port/SDL 1;2;4;5 Figure 8:SMT398 ComPorts connections...

  • Page 24: Shb

    12: Communication ports and the Texas Instrument Module Specification. SHB Connector The SMT398 includes 4 60-pin connectors to provide SHB communication to the outside world. All 60 pins of a SHB connector are routed to the Virtex II 3000 and above version of the SMT398.

  • Page 25: Shb Cable Assembly

    SHB cable assembly described in 0. The SMT398 in full configuration (0 Full configuration) provides 8 16-bit Sundance High Speed Buses (SHB) on 4 connectors and can support data rates of up to 200MHz.

  • Page 26: Global Bus

    Description Specification V input V input V output output High High Maximum voltage Minimum voltage -0.5 Impedance 50 Ohms Frequency The Frequency limitations are the ones of the Virtex II part fitted on the SMT398. Table 4: External clock specification...

  • Page 27: Power Supplies

    Version 1.1.1 Page 27 of 38 SMT398 User Manual Power Supplies The PCI specifications state that the maximum power allowed for any PCI board is 25 Watts, and represents the total power drawn from all power rails provided at the connector (+5V, +3.3v, +VI/O,+12V,-12V, +3.3Vaux).

  • Page 28: Dc/Dc Converter

    Version 1.1.1 Page 28 of 38 SMT398 User Manual DC/DC Converter This module is designed to provide up to 20A of low voltage supply to the FPGA from a single 5V input. The output voltage provided is a Vout of 1.5V.

  • Page 29: Verification Procedures

    Because the Virtex FF896 and FF1152 packages are footprint and pinout compatible, the SMT398 offers a high level of flexibility in the choice of the FPGA fitted. The FPGA fitted will influence the amount of usable resources on the board and of course the price.

  • Page 30: Full Configuration

    Full configuration In the full configuration, a Virtex II 3000, 4000, 6000 or 8000 is used and allows interfacing to ALL the memories and ALL I/Os available on the SMT398. The SMT398 comes in 3 main full configurations, highlighted in red in Table 6.

  • Page 31: Basic Configuration

    Basic configuration In the basic configuration, a Virtex II 1000, 1500, or 2000 is used and allows interfacing to part of the memories and I/Os available on the SMT398. Memories Only 2 Banks of ZBT RAM are available to the FPGA. The total amount of ZBT on board shown in Table 7 is to be divided amongst these 2 banks.

  • Page 32: Pcb Layout Details

    Version 1.1.1 Page 32 of 38 SMT398 User Manual PCB Layout Details Components placement Figure 10:SMT398 Components placement-Top view...

  • Page 33: Figure 11: Smt398 Components Placement-Bottom View

    Version 1.1.1 Page 33 of 38 SMT398 User Manual Figure 11: SMT398 Components placement-Bottom view U1 : Xilinx FPGA U2: Xilinx CPLD U3: ZBTRAM Bank1 U4: ZBTRAM Bank2 U5: ZBTRAM Bank3 U6: ZBTRAM Bank4 U10: QDR Bank1 U11: QDR Bank2 These 2 Banks share the same address lines (See Figure 7:SMT398 QDR Width expansion arrangement.)

  • Page 34: Headers Pinout

    Version 1.1.1 Page 34 of 38 SMT398 User Manual Headers Pinout SHB Header Figure 12: Top View QSH 30...

  • Page 35: Shb Pinout (Lvttl Only).(J8-J9-J10-11)

    Version 1.1.1 Page 35 of 38 SMT398 User Manual SHB Pinout (LVTTL only).(J8-J9-J10-11) QSH Pin QSH Pin number number USERDEF0 USERDEF1 USERDEF2 USERDEF3 USERDEF0 USERDEF1 USERDEF2 USERDEF3 Table 8: SHB interfaces table. 32-bit 16-bit Interface interface...

  • Page 36: Jtag/Multilinx Headers

    Version 1.1.1 Page 36 of 38 SMT398 User Manual JTAG/Multilinx headers The JTAG/Multilinx headers have the following pinout: BUSY INIT RDWR PROG DONE TRIG CCLK 3.3V Figure 13: Top View of JTAG/Multilinx headers JTAG/Boundary scan pinout (J13) Name Pin Function Connections Power.

  • Page 37: Multilinx Selectmap Pin Descriptions (J12-J13)

    Version 1.1.1 Page 37 of 38 SMT398 User Manual MultiLINX SelectMap Pin Descriptions (J12-J13) Signal Pin Function Name Power. Supplies VCC to cable (Works at multiple voltages 5V, 3.3V, and 2.5V). Ground. Supplies ground reference to cable. CCLK Configuration Clock is the configuration clock pin, and the default clock for readback operation.

  • Page 38: Safety

    Version 1.1.1 Page 38 of 38 SMT398 User Manual D0-D7 2,4,6,8 Data Bus — This pin is used for Virtex SelectMAP Mode. An 8-bit data bus supporting the SelectMAP and Express 10,12, configuration modes. 14,16 CS0 (CS) Chip Select — CS on the Virtex.

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