Sundance Spas SMT370v2 User Manual
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Sundance Spas SMT370v2 User Manual

Sundance Spas SMT370v2 User Manual

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SMT370v2
User Manual
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

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Summary of Contents for Sundance Spas SMT370v2

  • Page 1 SMT370v2 User Manual User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999...

  • Page 2: Revision History

    Version 1.0 Page 2 of 44 SMT370v2 User Manual Revision History Date Comments Engineer Version 14/02/03 First release Details added about registers and external 08/03/03 signals – figure references – examples. FPGA Firmware changed – ADC/DAC Triggers 31/03/03 and ADC decimators added – SHBA and B 16...

  • Page 3: Table Of Contents

    Version 1.0 Page 3 of 44 SMT370v2 User Manual Table of Contents Revision History......................2 Table of Contents ....................... 3 Table of figures......................4 Contacting Sundance....................5 Notes.......................... 5 Precautions......................... 5 Block Diagram......................7 Architecture Description..................... 8 Virtex FPGA.

  • Page 4: Table Of Figures

    Version 1.0 Page 4 of 44 SMT370v2 User Manual Power Consumption....................25 Register settings....................... 26 Register 0x0 – DAC Register (report to AD9777 datasheet for more details)..26 Register 0x1 – DAC register (report to AD9777 datasheet for more details)..27 Register 0x2 –...

  • Page 5: Contacting Sundance

    SMT370v2 User Manual Contacting Sundance. You can contact Sundance for additional information by sending email to support@sundance.com. Notes. SMT370 denotes in this document SMT370v2. SHB stands for Sundance High-speed Bus. CommPort denotes an 8-bit communication port following the TI C4x standards. Precautions...
  • Page 6 Page 6 of 44 SMT370v2 User Manual Outline description. The SMT370v2 is a dual high-speed ADC/DAC module offering the following features: - Two 14-bit ADCs (AD6645-105) sampling at up to 105MHz, - Dual 16-bit TxDAC (AD9777) sampling at up to 400MHz (interpolation),...

  • Page 7: Block Diagram

    Version 1.0 Page 7 of 44 SMT370v2 User Manual Block Diagram. The following diagram shows the architecture of the SMT370v2. 3 Power J2 Bottom Primary TIM supply Connector LEDs ‘FPGA configured’ Trig On-board Oscillator Trig 50 MHz AC or DC...

  • Page 8: Architecture Description

    Version 1.0 Page 8 of 44 SMT370v2 User Manual Architecture Description. The module consists of a Xilinx Virtex-II FPGA, two Analog Devices (14-bit monolithic sampling Analog-to-Digital converters) AD6645 and one Analog Devices AD9777 (Dual TxDAC+ Digital-to-Analog converter). AD6645 is a 14-bit monolithic sampling analog-to-digital converter. The chip provides CMOS-compatible digital outputs.

  • Page 9: Virtex Fpga

    Version 1.0 Page 9 of 44 SMT370v2 User Manual Two Communication links (CommPorts) following the Texas Instrument C4x standard are connected to the FPGA and will be used to receive control words or for other purpose. They can achieve transfers at up to 20Mbytes/s.

  • Page 10: Shb

    Version 1.0 Page 10 of 44 SMT370v2 User Manual SMT365 for instance. Please report to the part dealing with CommPorts in this document for more details. SHB. The SMT370 provides 2 full SHB (Sundance High-speed Bus) connectors, labelled SHBA (J3) and SHBB (J4) – see Figure 9 - Connector Location..

  • Page 11: Clock Management

    Version 1.0 Page 11 of 44 SMT370v2 User Manual reading it back continuously and sending data out to the DAC. This generator is controlled via bits in the control registers. It can be loaded, started and stopped by setting bits. For more details, see further in the documentation, the part dealing with control registers.

  • Page 12: Leds

    Version 1.0 Page 12 of 44 SMT370v2 User Manual LEDs. Seven LEDs (Figure 9 - Connector Location.)are available on the board. Four (denoted 1, 2, 3 and 4 on the PCB – top left) of them, green, are driven by the FPGA.

  • Page 13: Sundance High-Speed Bus

    Version 1.0 Page 13 of 44 SMT370v2 User Manual Figure 2 - CommPort interface data path. Sundance High-speed Bus. Both buses are identical and 60-bit wide. SHBs are parallel communication links for synchronous transmissions. Each SHB can be divided into two independent 8-bit buses. Each 8-bit bus includes a clock and three control signals: write enable, request and acknowledge.

  • Page 14: Adc Performance

    Version 1.0 Page 14 of 44 SMT370v2 User Manual ADC Performance. Description Specification Analogue inputs Maximum voltage 1.1 Volts peak-to-peak (AC coupling) 2.2 Volts peak-to-peak (DC coupling) Impedance 50 Ω Bandwidth 0-250 MHz - (No anti-aliasing filter) External Clock Minimum voltage 0.2 Volt peak to peak minimum...

  • Page 15: Figure 5 - Fft Adc Channel - On-Board Clock

    Version 1.0 Page 15 of 44 SMT370v2 User Manual The following graphs gives the average FFT of sixteen 16K-FFTs processed after capturing data from Channel B – The on-board sampling frequency set to 100 MHz – A 20MHz sine signal is fed to the board. The test has been performed without any input filter (which explains the second peak due to harmonics) at all and with a 35dBc harmonic performance signal generator.

  • Page 16: Dac Performance

    Version 1.0 Page 16 of 44 SMT370v2 User Manual DAC Performance. Description Specification Analogue outputs Maximum voltage 1 Volt peak-to-peak Impedance 50 Ω Bandwidth External Clock Minimum voltage 0.2 Volt peak to peak minimum Impedance 50 Ω Frequency range 20-160 MHz – low jitter...

  • Page 17: Figure 7 - Fft Dac Channel

    Version 1.0 Page 17 of 44 SMT370v2 User Manual The following capture shows a 5MHz signal generated by the DAC under an on- board sampling clock of 160MHz. Note that no output filter was used during the capture. Figure 7 - FFT DAC Channel.

  • Page 18: Shb Pinout

    Version 1.0 Page 18 of 44 SMT370v2 User Manual SHB pinout. Signal Signal Signal CLK0 D20/ WEN1 D21/ REQ1 D22/ ACK1 D23/ CLK2 D44/ WEN3 D45 REQ23 D46/ ACQ3 D47/ CLK3 D8/ WEN0 D9/ REQ0 D10/ ACK0 D11/CLK1 D32/WEN2 D33/REQ2...

  • Page 19: Fpga Pinout

    Version 1.0 Page 19 of 44 SMT370v2 User Manual The default FPGA firmware implements 2 16-bit interfaces. FPGA Pinout. ########################################### NET "FREQ_S_DATA_ADCs" LOC = "B19" NET "FREQ_S_DATA_DAC" LOC = "B17" NET "FREQ_S_LOAD_ADCs" LOC = "A18" Constraint File Virtex SMT370 NET "FREQ_S_LOAD_DAC" LOC = "C17"...
  • Page 20 Version 1.0 Page 20 of 44 SMT370v2 User Manual NET "ADC_TRIG" LOC = "T21" NET "ZBT_DQa<1>" LOC = "A9" NET "IIOF_0" LOC = "V11" NET "ZBT_DQa<0>" LOC = "B9" NET "ADCA_RDY_GCLK" LOC = "W11" NET "ZBT_CS2" LOC = "B13" NET "ZBT_nOE" LOC = "D14"...
  • Page 21 Version 1.0 Page 21 of 44 SMT370v2 User Manual NET "CONF_INIT" LOC = "AA19" NET "DAC_P1B<14>" LOC = "Y21" NET "CONF_DIN" LOC = "V18" NET "DAC_P1B<15>" LOC = "Y22" NET "CLOCK" LOC = "D11" NET "DAC_P2B<0>" LOC = "W13" NET "CP3_ACK" LOC = "V21"...
  • Page 22 Version 1.0 Page 22 of 44 SMT370v2 User Manual NET "SHBB<39>" LOC = "M19" NET "SHBA<55>" LOC = "V2" NET "SHBB<38>" LOC = "M20" NET "SHBA<54>" LOC = "V1" NET "SHBB<37>" LOC = "M21" NET "SHBA<53>" LOC = "U2" NET "SHBB<36>" LOC = "L22"...

  • Page 23: At Power-Up And On Reset

    Version 1.0 Page 23 of 44 SMT370v2 User Manual NET "SHBA<11>" LOC = "J1" NET "SHBA<5>" LOC = "H3" NET "SHBA<10>" LOC = "J2" NET "SHBA<4>" LOC = "H4" NET "SHBA<9>" LOC = "J3" NET "SHBA<3>" LOC = "J6" NET "SHBA<8>" LOC = "J4"...

  • Page 24: Connector Position

    Version 1.0 Page 24 of 44 SMT370v2 User Manual Connector position. Figure 9 - Connector Location. The diagram below gives the position and the meaning of the connectors that the customer is likely to use.

  • Page 25: Operating Conditions

    Version 1.0 Page 25 of 44 SMT370v2 User Manual Operating conditions. Safety The module presents no hazard to the user. The module is designed to operate within an enclosed host system that provides adequate EMC shielding. Operation within the EU EMC guidelines is only guaranteed when the module is installed within an appropriate host system.

  • Page 26: Register Settings

    Version 1.0 Page 26 of 44 SMT370v2 User Manual Register settings. Register 0x0 – DAC Register (report to AD9777 datasheet for more details). Description number Bit 31 Bit 30 Bit 29 Bit 28 Bit 27-24 Not Used. SDIO bidirectional. ‘0’=Input or ‘1’=I/O - To be set to ‘0’ when using default Bit 23 firmware.

  • Page 27: Register 0X1 - Dac Register (Report To Ad9777 Datasheet For More Details)

    Version 1.0 Page 27 of 44 SMT370v2 User Manual Register 0x1 – DAC register (report to AD9777 datasheet for more details). Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 27-18 Not Used. Bit 17 PLL Divide (Prescaler) Ratio.

  • Page 28: Register 0X2 - Dac Register (Report To Ad9777 Datasheet For More Details)

    Version 1.0 Page 28 of 44 SMT370v2 User Manual Register 0x2 – DAC register (report to AD9777 datasheet for more details). Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 27-20 Not Used. Bit 19 IDAC Coarse Gain Adjustment...

  • Page 29: Register 0X3 - Dac Register (Report To Ad9777 Datasheet For More Details)

    Version 1.0 Page 29 of 44 SMT370v2 User Manual Register 0x3 – DAC register (report to AD9777 datasheet for more details). Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 27-24 Not Used. Bit 23 QDAC Fine Gain Adjustment...

  • Page 30: Register 0X4 - Dac Register (Report To Ad9777 Datasheet For More Details)

    Version 1.0 Page 30 of 44 SMT370v2 User Manual Register 0x4 – DAC register (report to AD9777 datasheet for more details). Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 27-24 Not Used. Bit 23 QDAC I Direction.

  • Page 31: Register 0X5 - Clock Management

    Version 1.0 Page 31 of 44 SMT370v2 User Manual Register 0x5 – Clock management. Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Clock Selection ADCA (ADCA - ‘0’=Internal; ‘1’=External) Bit 26 Clock Selection ADCB (ADCB - ‘0’=Internal; ‘1’=External) Bit 25 Clock Selection DAC (‘0’=Internal;...

  • Page 32: Figure 10 - Clock Routing

    Version 1.0 Page 32 of 44 SMT370v2 User Manual With 500 < M < 250 (binary encoding) and N can take one of = (M/N) MHz - Synthesized the following values: 1, 1.5, 2, 3, 4, 6, 8 or 12 (for respectively “000”… ”111”...

  • Page 33: Register 0X6 - Channel Selection - Triggers - Decimator

    Version 1.0 Page 33 of 44 SMT370v2 User Manual Register 0x6 – Channel selection – Triggers – Decimator for ADCs. Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Not Used. Bit 26 Bit 25 Bit 24 Decimation Factor Channel B –...

  • Page 34: Register 0X7 - Dac Control - Pattern Generator

    Version 1.0 Page 34 of 44 SMT370v2 User Manual Register 0x7 – DAC control – Pattern generator. Bit number Description Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 External Trigger Level (‘0’=Active low; ‘1’=Active high) Bit 26 External Trigger Enable (‘0’=External Trigger Disabled; ‘1’=Enabled) Bit 25 Channel A Enable (‘0’=Disabled;...
  • Page 35 Version 1.0 Page 35 of 44 SMT370v2 User Manual Direct Transfer: When Direct To DAC mode selected, data are written into a FIFO (that can contain up to 512 words of 16 bits) under the SHB clock and sent out to the DAC directly under the DAC sampling clock.

  • Page 36: Register 0Xe - Dac Register Read Back

    Version 1.0 Page 36 of 44 SMT370v2 User Manual Register 0xE – DAC Register Read back. Description number Bit 31 Bit 30 Bit 29 Bit 28 Bit 27-0 Not Used. By sending this control word, the FPGA reads back the DAC register from the AD9777. Once this control word has been sent on CP3 of the 370, expect to receive 15 CommPort word in return on the same link.

  • Page 37: Register 0Xf - Serial Interfaces Load

    Version 1.0 Page 37 of 44 SMT370v2 User Manual Register 0xF – Serial Interfaces load. Description number Bit 31 Bit 30 Bit 29 Bit 28 Bit 27-0 Not Used. The DAC and the clock synthesizers have all a S erial P ort I nterface. By sending this control word, the FPGA serialises Register 0 to 5 and send them to the DAC and both clock synthesizers.

  • Page 38: Example Code For 3L Diamond - Configuring Registers/Data Capture/Direct2Dac

    Version 1.0 Page 38 of 44 SMT370v2 User Manual Example code for 3L Diamond – Configuring registers/Data capture/Direct2DAC. //************************************************* // SMT 370 - Configuring DAC and clock synthesizers //************************************************* // This example code is to compile with 3L Diamond V2.1.6...
  • Page 39 Version 1.0 Page 39 of 44 SMT370v2 User Manual #define SINE_RATIO 8 // Main // main() int index; int ReadBackWord; int i; static volatile unsigned int *SMT365CP0_STAT=(volatile unsigned int*)0x90004000; // SMT 365 CommPort0 Status register // SDB (=half SHB = 16-bit interface) and memory allocation int *BufferA = memalign(128, 4*DATA_SIZE);...
  • Page 40 Version 1.0 Page 40 of 44 SMT370v2 User Manual link_out_word(REGISTER_5, COMM_PORT0); link_out_word(REGISTER_6, COMM_PORT0); link_out_word(REGISTER_7, COMM_PORT0); printf("Passing Register values to DAC and clock synthesizers \n"); link_out_word(REGISTER_F, COMM_PORT0); par_printf("Reading Back DAC SPI Registers \n"); link_out_word(REGISTER_E, COMM_PORT0); index=0; printf("Waiting for words \n"); printf("CP0 status : %08x\n ", (*SMT365CP0_STAT));...

  • Page 41: Example Code For 3L Diamond - Configuring Registers/Data Capture/Pattern Generator

    Version 1.0 Page 41 of 44 SMT370v2 User Manual Example code for 3L Diamond – Configuring registers/Data capture/Pattern Generator. This code can be used with system where the DAC outputs are connected directly to the ADC inputs. The DAC is set to work continuously in Pattern Generator mode.
  • Page 42 Version 1.0 Page 42 of 44 SMT370v2 User Manual #define REGISTER_F 0xf0000000 // Reg F : Load SPI DAC and clock synthesizers #define CP0_STAT_IFE (unsigned int)0x000F0000 // SMT 365 CommPort 0 Input fifo status register - Fifo empty #define COMM_PORT0...
  • Page 43 Version 1.0 Page 43 of 44 SMT370v2 User Manual printf("Address BufferC : %08x\n ", BufferC); printf("Address BufferD : %08x\n ", BufferD); printf("Make sure buffers are in Internal Memory - allow better performance\n"); printf("\n SMT365 + SMT370 \n"); printf(" ================\n"); printf("Loading Registers \n");...
  • Page 44 Version 1.0 Page 44 of 44 SMT370v2 User Manual link_out_word(REGISTER_7, COMM_PORT0); printf("Capturing data from ADCs\n"); SMT_SDB_Control(Sdb0, SDB_CLRIF); // Clear input fifo prior to read operation SMT_SDB_Read (Sdb0, 4*PATTERN_SIZE, BufferC); // size in byte SMT_SDB_Control(Sdb1, SDB_CLRIF); // Clear input fifo prior to read operation SMT_SDB_Read (Sdb1, 4*PATTERN_SIZE, BufferD);...

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