Fpga Configuration; Electrical Interface; The Service Cpld; Figure 2: Fpga Configuration In Selectmap Mode Using Cpld - Sundance Spas SMT398 User Manual

Version 1.1.1

FPGA Configuration

The FPGA can be configured 2 different ways:
• Using ComPort 3 to provide the bitstream. (See
• Using the on-board JTAG header and Xilinx JTAG programming tools. (See
FPGA in system
•
At power up the FPGA is not configured.
LED L5 (See Figure 10:SMT398 Components placement-Top
hand corner of the picture) will be lit upon FPGA configuration.

Electrical Interface

The service CPLD

The CPLD allows for FPGA configuration in slave SelectMap mode.
At power up or after a Reset of the SMT398, the CPLD is configured and
implements a ComPort link receiver on ComPort 3.
The CPLD is connected to ComPort number 3 of the SMT398 TIM connector.
Consequently, the ComPort on the other end of the link must be configured as
transmitter at power-up or after reset, i.e. ComPort channels 0, 1, or 2.
The typical SMT398 user does not need an in depth understanding of the
configuration sequence and of the Virtex II. However, for the purpose of debugging
and designing for the SMT398 an overview of the necessary configuration protocol
and bitstream formatting is recommended.
Therefore, this section describes the CPLD functions, the Virtex II bitstream format
and the necessary bitstream re-formatting when downloading the bitstream to the
FPGA via CPLD + ComPort 3.

Figure 2: FPGA configuration in SelectMap mode using CPLD

illustrate the descriptions below.
Page 10 of 38
programming)
SMT398 User Manual
The service CPLD)
view, bottom right
provides waveforms to