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Figure 4: V II Configuration Bitstream Word Format
As a result, to be able to download the bitstream to the FPGA using ComPort3 +
CPLD, the Virtex II configuration bitstream must be re-formatted to match the
ComPort word standard.
Bitstream Re-formatting
The re-formatting consists in inverting the bits in a byte and the bytes in a 32-bit
word.
Further, the .bit files contain a header section before the pad word and
synchronization word. The download function FPGAFullConfiguration() from the
SMT6500 package searches for the synchronization sequence and skips the header.
CPLD code versions
• V1.0: Initial release that only receives the bitstream and configures the FPGA.
FPGAResetn is NOT implemented and ComPort 3 is NOT released once the
FPGA is configured.
• V2.0 Indicated on a sticker on the CPLD. The CPLD implements the functions
described above except
• V2.1 Indicated on a sticker on the CPLD. V2.0 + the CPLD implements the
reconfiguration feature described in
FPGA
The module can be fitted with a XC2V1000, XC2V1500, XC2V2000, XC2V3000,
XC2V4000, XC2V6000 or XC2V8000.
The FPGA comes in two pinout/footprint compatible packages: flip-chip FF896 and
FF1152.
The choice of FPGA will be price/performance driven. The following table shows the
main FPGA characteristics.
The choice of the FPGA also determines which board architecture you will get
(amount of logic available, speed, number and type of I/Os, on-board Memory size
and type). For a complete list of the different board architectures, please consult: 0
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