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SMT370v2 User Manual
Two Communication links (CommPorts) following the
Texas Instrument C4x standard
are connected to the FPGA and will be used to receive control words or for other
purpose. They can achieve transfers at up to 20Mbytes/s.
Two full SHB connectors (60-pin) are accessible from the FPGA. The first connector
(SHBA) is set as output only and is dedicated for sending out samples coming from
the ADC. The second connector (SHBB) is set as input only to receive samples,
which are redirected to the DAC. Please refer to the
SHB specifications
for more
details about ways connectors can be configured. Both SHB can be implemented as
either two 16-bit interfaces or a single 32-bit interface. In the case of a 32-bit
interface, both ADCs must receive the same sampling clock signal.
Four LEDs are driven by the FPGA. Four LVTTL I/Os for general purpose are also
available. No clamping diodes to 3.3 Volts and ground are available on the board to
avoid damaging pads on the FPGA. It is therefore to the customer to male sure the
signals connected to these I/Os are LVTTL and don't show any overshoots.
External Clock, trigger and analogue input signals are all single-ended. External
connections to the board are all 50-Ohm terminated. External triggers have clamping
diodes to 3.3V and to Ground to avoid damaging the FPGA they are connected to.
A global reset signal is mapped to the FPGA from the top TIM connector to reset the
FPGA and reload the FPGA
Virtex FPGA.
The SMT370 is populated with a Xilinx Virtex FPGA (XC2V1000-6FG456). This
device controls major functions on the module, like CommPorts and SHB
communications, data flows to and from the converters, memory and clock
generation.
This FPGA needs being configured after power-up and after a module reset. This
operation is possible thanks to the on-board Xilinx PROM. This operation can be
done automatically when jumper J8 (Figure 9 - Connector Location.)is fitted. If it is
not fitted, no configuration is loaded into the FPGA and allows therefore the user to
program the FPGA via JTAG with no possible conflict.
Ten control registers are implemented into this FPGA to set up converters, their data
format, clock synthesizers, CommPort, SHB and memory transfers. Some more
details are given in the next parts of this document.
The FPGA is serially programmed using the dedicated pins. The PROM is originally
programmed with a default bit stream, which implements all features mentioned in
this document.
Communication Ports (CommPorts).
The SMT370 provides 2 CommPorts: 0 and 3. The default bit stream provided
implements CommPort 3 (Input at reset) to load control registers. A physical
connection to a CommPort 0, 1 or 2 (Output at reset) is therefore necessary, to an
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