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Block description
This section describes the major blocks of the SMT351 board.
FPGA
The SMT351 board uses a Xilinx Virtex II Pro (XC2VP7, XC2VP20 or XC2VP30) to
control the data flow between the SMT351 board and external devices. The FPGA is
also used to implement the SHB, comport and DDR SDRAM interfaces.
The FPGA is configured via a 6-pin JTAG header or from a user-selectable ComPort.
Memory
The SMT351 board contains sixteen 133 MHz DDR SDRAM components (from
Micron or Samsung) that provide 1 GB of storage capacity.
The DDR SDRAM is a high-speed CMOS, dynamic random-access memory.
CPLD
A Xilinx CPLD is used to manage configuring the FPGA. It connects to the six
comports available on the module.
Sundance High Speed Bus
Unidirectional 32-bit SHB interfaces are implemented on SHB connectors. They run
at 100 MHz, giving a 400MB/s data rate thru the SMT351.
SHB A implements a receiver-only interface while SHB B implements a transmitter-
only interface.
Please refer to the
Comports
The SMT351 provides up to 6 comports, which are used to receive the configuration
bitstream and commands to the FPGA. Once configured, the SMT351 is controlled
via comport 3.
The number of comports provided depends on the type of FPGA fitted on the board:
• XC2VP7 provides 3 comports: 0, 1 and 3.
• XC2VP20 or XC2VP30s provides 6 comports.
TTL I/Os.
Four TTL I/Os supporting LVTTL signals are connected directly to the FPGA (JP2).
These I/Os are not used by Sundance firmware and are available for customer use.
You must ensure that any lines you connect to these pins are LVTTL compatible in
order to protect the FPGA pads, as lines are not clamped.
See
JP2 pinout
section for more details.
SUNDANCE SHB specification
Page 9 of 24
for more details.
SMT351 User Manual
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