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Version 1.1.1
Verification Procedures
The specification (design requirements) will be tested using the following:
1) Power module test.
2) FPGA configuration using CPLD and/or JTAG connector.
3) ComPort transfers between a SMT335 and the SMT398.
4) ZBT and QDR memory tests.
5) SHB connector Pins Test
6) Global Bus transfers between SMT398 and SMT310Q onboard SRAM.
7) External clock I/O tested with scope.
Review Procedures
Reviews will be carried out as indicated in design quality document QCF14 and in
accordance with Sundance's ISO9000 procedures.
Validation Procedures
The validation procedure is happening during the verification procedure.
Test that all the memories are accessible by the FPGA as well as all the
communication links.
Circuit Diagrams
Ordering information:
Because the Virtex FF896 and FF1152 packages are footprint and pinout compatible,
the SMT398 offers a high level of flexibility in the choice of the FPGA fitted.
The FPGA fitted will influence the amount of usable resources on the board and of
course the price.
Currently, the SMT398 is available in 2 configurations: Basic and Full.
Page 29 of 38
SMT398 User Manual
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