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Version 1.1.1
You must make sure to use the SMT6500 package V1.0 and above (which contains
the VHDL for it).
Global bus
The global bus is compatible with the TIM standard.
The Global Bus Interface is a memory Interface that follows Texas Instruments'
TMS320C4x External Bus operation standard. Additional information on the standard
is available in the
TMS320C4x User's Guide
External Bus operation.
When Writing, the FPGA sends data across the global bus to the external device.
When Reading, the external device writes data across the global bus to the FPGA.
Clocks
An on-board oscillator provides a free running clock to the FPGA and CPLD. The
default is a 50Mhz oscillator but other frequencies can be provided upon request to
Sundance.
An external clock input/outptut is provided to the Virtex II FPGA via a 50 ohms MMBX
coax-connector.
These clocks can be de-skewed by the FPGA DCMs or output to other TIMs to
synchronise TIMs together.
Description
Maximum voltage
Minimum voltage
Impedance
Frequency
Table 4: External clock specification
Page 26 of 38
chapter 9:
V input
V
Low
output
Low
0.8
0.4
-0.5
50 Ohms
The Frequency limitations are the ones of
the Virtex II part fitted on the SMT398.
SMT398 User Manual
Specification
V input
V output
High
High
3.8
2.0
2.4
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