Table Of Contents - Sundance Spas SMT398 User Manual

Version 1.1.1

Table of Contents

Revision History.......................................................................................................... 2
Table of Contents ....................................................................................................... 3
Table of Figures.......................................................................................................... 5
Table of Tables........................................................................................................... 5
Physical Properties..................................................................................................... 6
Introduction................................................................................................................. 7
Related Documents ................................................................................................ 7
Block Diagram ............................................................................................................ 7
Mechanical Interface: TIM Standard........................................................................... 8
SMT398 Installation.................................................................................................... 8
SMT398 Alone ........................................................................................................ 8
SMT398 + DSP TIM................................................................................................ 9
FPGA Configuration ................................................................................................. 10
Electrical Interface .................................................................................................... 10
The service CPLD ................................................................................................. 10
CPLD Functions ................................................................................................ 11
Virtex II Bitstream Format.................................................................................. 14
Bitstream Re-formatting..................................................................................... 15
CPLD code versions.......................................................................................... 15
FPGA .................................................................................................................... 15
FPGA in system programming .......................................................................... 17
JTAG/Boundary Scan........................................................................................ 18
Configuring with MultiLINX ................................................................................ 19
FPGA Readback and Partial reconfiguration..................................................... 19
Memory ................................................................................................................. 20
Pipelined ZBTRAM ............................................................................................ 20
QDR (Quad Data Rate) ..................................................................................... 21
ComPorts .............................................................................................................. 23
SHB ...................................................................................................................... 24
SHB Connector ................................................................................................. 24
SHB Cable Assembly ........................................................................................ 25
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