Sundance Spas SMT332 User Manual
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Sundance Spas SMT332 User Manual

Sundance Spas SMT332 User Manual

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SMT332/372
User Manual
User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999

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  • Page 1 SMT332/372 User Manual User Manual (QCF42); Version 3.0, 8/11/00; © Sundance Multiprocessor Technology Ltd. 1999...

  • Page 2: Revision History

    Version 1.3 Page 2 of 36 SMT332/372 User Manual Revision History Date Comments Engineer Version 7/3/00 Original Revision 9/3/00 General reorganisation 14/08/00 Comport data rate (safe mode not working) and samples code using DMA 23/2/01 Corrected FIFO status memory space.

  • Page 3: Outline Description

    Version 1.3 Page 3 of 36 SMT332/372 User Manual Outline Description The SMT332/372 is a size 1 TIM offering the following features: SMT332: TMS320C6201 processor running at 200MHz SMT372: TMS320C6701 processor running at 166MHz Four communications ports (approx 15M bytes/s)

  • Page 4: Table Of Contents

    Version 1.3 Page 4 of 36 SMT332/372 User Manual Table of Contents Revision History....................2 Outline Description....................3 Table of Contents....................4 Block Diagram ..................... 6 Architecture Description..................6 TMS320C6201/6701 (‘C6x01)................7 Boot Mode ....................... 7 EMIF Control Registers ..................8 SBSRAM ......................
  • Page 5 Version 1.3 Page 5 of 36 SMT332/372 User Manual Serial Ports ....................35 FPGA Configuration ................... 36...

  • Page 6: Block Diagram

    J2 Secondary Connector Architecture Description The SMT332 TIM consists of a Texas Instruments TMS320C6201 running at 200MHz and the SMT372 has a TMS320C6701 running at 166MHz. The TIM is populated with 512k bytes of SBSRAM (synchronous burst SRAM) and 16M bytes of SDRAM (synchronous DRAM) offering a total memory capacity of 16.5M bytes.

  • Page 7: Tms320C6201/6701 ('C6X01)

    Boot Mode The ‘C6x01 is capable of booting in several different modes. On the SMT332/372, the boot mode is defined such that the ‘C6x01, after reset, will copy the first 64kb of flash data into internal program RAM, and then execute that code.

  • Page 8: Emif Control Registers

    Version 1.3 Page 8 of 36 SMT332/372 User Manual EMIF Control Registers The ‘C6x01 contains several registers which control the operation of the external memory interface (EMIF). Each memory space (CE0 to 3) has an independent register, and in addition, there is a global control register.

  • Page 9: Flash

    For operation in a TIM 40 environment, 4 communication (comm) ports are provided. The comm ports on the SMT332/372 will interface to any standard ‘C4x comm port. The comm ports can operate in two modes. The first mode is for the ‘C6x01 to transfer data to the port directly using a polling technique.
  • Page 10 Version 1.3 Page 10 of 36 SMT332/372 User Manual The following table defines the bit functions within the status register. Status Register Bit Function Comm port 0 rx data available Comm port 0 tx buffer empty Comm port 3 rx data available...

  • Page 11: Interrupts

    Version 1.3 Page 11 of 36 SMT332/372 User Manual Interrupts The interrupts to the ‘C6x01 can be produced by comm port status change DMA completion FIFO flag status change external IIOF and TCLK signals present on the TIM connector There are two registers that control the interrupt enabling. Interrupt Control register A (ICRA) provides the first stage of interrupt selection, followed by Interrupt Control Register B (ICRB).
  • Page 12 Version 1.3 Page 12 of 36 SMT332/372 User Manual Address (hex) Function 0160 0014 Interrupt control register A Interrupt Control Register Bit Function 1 & 0 00: Enable Comm Port 0 rx data available to INT4 01: Enable Comm Port 0 tx data available to INT4...
  • Page 13 Version 1.3 Page 13 of 36 SMT332/372 User Manual Address (hex) Function 0158 0000 Interrupt control register B - ICRB (write only) Interrupt Control Register Bit Function Clear to enable FIFO Channel A, flag to INT4. Set to enable CINT4 to INT4.
  • Page 14 Version 1.3 Page 14 of 36 SMT332/372 User Manual The functions of ICRA and ICRB are shown diagrammatically below: ICRB8 ICRB13:12 ICRB9 ICRB10 ICRB15:14 ICRB11...

  • Page 15: Nmi

    This signal, on a standard ‘C4x based TIM, is connected to the processor’s IIOF3 pin. On the SMT332/372, the CONFIG signal is asserted after power on, and can be released by writing to the interrupt control register A (address 0x0160 0014) with bit 8...

  • Page 16: Fifo Data Input/Output

    SMT332/372 User Manual FIFO Data Input/Output The SMT332/372 provides a high bandwidth data input facility for up to 32-bit data. The inputs are split in two 16-bit channels. Both channels are identical and may be referred to as Channel A & B with Channel A representing the least significant 16-bits and B the most significant 16-bits of the 32-bit word.
  • Page 17 Version 1.3 Page 17 of 36 SMT332/372 User Manual same address as that needed for ‘both ports read’ function, but as we have switched memory types (SDRAM to ASYNC) then the FIFOs are not actually accessed at all. The FIFO flag positions need to be serially loaded. Data bit D19 is used for port A FIFO, and data bit D23 for port B.

  • Page 18: Global Expansion

    The ‘C6x01’s EMIF is not directly compatible with the TIM global connector standard. This is due primarily to the ‘C6x01 bus speed and bus voltage levels. The SMT332/372 does implement a fully compatible TIM global connector through the use of an EPLD.

  • Page 19: Clock Speed

    Version 1.3 Page 19 of 36 SMT332/372 User Manual Clock Speed The ‘C6x01 clock speed must be set in conjunction with consideration to EMIF device speeds. Under most circumstances, the ‘C6201 would be set to 200MHz and have an SBSRAM speed equal to the core speed. The ‘C6701 would be set to 166MHz.

  • Page 20: Memory Map (Map 1)

    Version 1.3 Page 20 of 36 SMT332/372 User Manual Memory Map (MAP 1) Starting Address RESOURCE Refer to Internal Program RAM 0000 0000 Reserved 0001 0000 External Memory Space CE0 SBSRAM 0040 0000 512kb SBSRAM External Memory Space CE1 Flash...

  • Page 21: Example Code

    Version 1.3 Page 21 of 36 SMT332/372 User Manual Example Code The following examples illustrate the use of the FIFOs. FIFO Reset // make a copy of the current EMIF CE3 mode old_ce3 = *EMIF_CE3_CTRL; // This writes to the ‘C6x01 internal EMIFCE3 control register // at address 0x01800014, and sets it to async mode *EMIF_CE3_CTRL = 0xffff3f23;...
  • Page 22 Version 1.3 Page 22 of 36 SMT332/372 User Manual Programmable Flags Example code is included here to show how to configure the programmable flag offsets of the FIFOs. Both the FIFO control register and the FIFO data is accessible using ‘C6x memory space CE3.
  • Page 23 Version 1.3 Page 23 of 36 SMT332/372 User Manual Data Aquisition This is a simple example of how to capture data from the SDB into SDRAM. // The flags are read at address 0x01580000 volatile unsigned *flags = (unsigned *)0x01580000;...
  • Page 24 Version 1.3 Page 24 of 36 SMT332/372 User Manual // Wait for DMA to finish (could be linked to the DMA TCINT) while((*DMA_PRI_CRTL0 & 0xc)!=0); // Then setup the DMA to move the data from internal data memory // into external SDRAM *DMA_PRI_CRTL0 = 0x01000050;...
  • Page 25 Version 1.3 Page 25 of 36 SMT332/372 User Manual Global Bus Example This example shows the ‘C6x01 DMA controller being used to transfer data via the PCI bus. In this example, the target is host display memory. Note that the host display memory must be linear (not an old PC-AT style VGA type card).
  • Page 26 Version 1.3 Page 26 of 36 SMT332/372 User Manual for(loop=0;loop!=256;loop++) { for(blocks=0;blocks!=16;blocks++) { // Set the 331 page register to point to the address register // on the SMT320. This is at address 0xC0400000. global=(unsigned *)0x01780000; *global=0xc040; // Then we set the SMT320 address register to the start of the // host’s display memory.
  • Page 27 Version 1.3 Page 27 of 36 SMT332/372 User Manual Comport transfer example using DMA This examples shows how to transfer data over a comport between 2 TIMs using DMA. #define FRAME_SIZE 0x0400 //0x0400=1024=1KWord <=> 4KByte #define N_FRAME 0x0400 #define TRANSFER_SIZE...
  • Page 28 Version 1.3 Page 28 of 36 SMT332/372 User Manual if (*(SDRAM0+data) != data) Errors++; printf("Sent: 0x%X Received: 0x%X\n",data,*(SDRAM0+data)); /***** DSP2 : TRANSMIT - DMA SETTINGS *****/ *EMIF_CE1_CTRL = 0x8238c823; *SMT331INTCTRL = 0x0004; //Slow mode - Comport3 TX data to INT5 *DMA_PRI_CTRL0 = 0x01280030;...

  • Page 29: Code Composer

    Using the SMT6000 supplied tools, a .out file is easily generated. The Server Loader will read the .out file, decode it, and then transmit it via comm port to the SMT332/372. The Server Loader includes a COFF decoder, and translates this into ‘C4x style boot code.

  • Page 30: Mechanical Configuration

    Version 1.3 Page 30 of 36 SMT332/372 User Manual Mechanical Configuration...

  • Page 31: Operating Conditions

    The SMT332/372 TIM is in a range of modules which must be supplied with a 3.3v power source. In addition to the 5v supply specified in the TIM specification, these new generation modules require the additional 3.3v supply...

  • Page 32: Connectors

    Version 1.3 Page 32 of 36 SMT332/372 User Manual Connectors Tim Connector Position The following drawings illustrate the respective positions of the TIM connectors and the FIFO data optional connector. PRIMARY CONNECTOR MOTHERBOARD GLOBALCONNECTOR...
  • Page 33 DIN15 FLAG RESET The SMT332/372 has two SDB connectors. FIFO channel A uses connector labelled HDR1, and channel B uses HDR2. RESET and WEN are active low. RESET will cause a partial FIFO reset only. It will not alter the programmable flag positions.
  • Page 34 Version 1.3 Page 34 of 36 SMT332/372 User Manual Optionally, at build time, the module may be supplied with an 80-way connector mounted on the underside of the TIM. The pin-out of this connector is given here. Function Function WCLKA...

  • Page 35: Serial Ports

    Version 1.3 Page 35 of 36 SMT332/372 User Manual To design a custom carrier you will require the TIM specification and the following details of the header for the underside of the PCB. This connector is the same as the standard TIM carrier connectors, namely Hirose FX4 series: Underside Header: FX4A1-80P-1.27SV...

  • Page 36: Fpga Configuration

    Version 1.3 Page 36 of 36 SMT332/372 User Manual FPGA Configuration This device must be configured, by the ‘C6x01, before proper operation. To do this, the General Control Register (address 0x0150 0000) must have the PROG bit set, and then cleared. This register is defined here.

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