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Summary of Contents for Sundance Spas SMT351
- Page 1 SMT351 User Manual...
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Page 2: Revision History
Version 1.1 Page 2 of 24 SMT351 User Manual Revision History Date Comments Engineer Version 28/07/04 First revision... -
Page 3: Table Of Contents
Table of Contents ....................... 3 Introduction......................... 7 Description ......................7 Features........................7 Additional resources ....................7 Architecture description ....................8 SMT351 block diagram ................... 8 Block description..................... 9 FPGA ........................9 Memory ........................9 CPLD ........................9 Sundance High Speed Bus ..................9 Comports ........................ - Page 4 Version 1.1 Page 4 of 24 SMT351 User Manual Register definition..................... 18 FPGA reset register (0x00) ................... 18 Control register (0x02) ..................18 Software ........................19 SMT351_Config ....................19 Definition ......................19 Prototype ......................19 Parameters......................19 SMT351_Capture....................19 Definition ......................19 Prototype ......................
- Page 5 Page 5 of 24 SMT351 User Manual Table of Figures Figure 1: SMT351 board block diagram ..............8 Figure 2: SMT351 FPGA data flow................14 Figure 3: DDR SDRAM components bank organization........... 15 Figure 4: FPGA’s clock domains ................16 Figure 5: SMT351 connector locations ..............
- Page 6 Tables of Tables Table 1: LED description ..................10 Table 2: configuration comport selection..............12 Table 3: TIM CONFIG feature: SW1 settings ............13 Table 4: FPGA’s clock domains description ............. 16...
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Page 7: Introduction
Introduction Description The SMT351 card is a TIM format memory module that is able to store up to 1GB of data at 400MB/s. SMT351 modules can be cascaded to extend storage capability. The module is based on DDR SDRAM memory components running at up to 133 MHz. -
Page 8: Architecture Description
Page 8 of 24 SMT351 User Manual Architecture description SMT351 block diagram Figure 1 shows a block diagram of the SMT351 board. Refer to the following section for additional information on the major blocks. J1 Top Primary TIM 3 Power... -
Page 9: Block Description
This section describes the major blocks of the SMT351 board. FPGA The SMT351 board uses a Xilinx Virtex II Pro (XC2VP7, XC2VP20 or XC2VP30) to control the data flow between the SMT351 board and external devices. The FPGA is also used to implement the SHB, comport and DDR SDRAM interfaces. -
Page 10: Leds
Control Register bit 15 is high. On when memory is being read back. JTAG The SMT351 includes a 6-pin JTAG header (2mm DIL header), which allows re- programming the FPGA using a cable such as Xilinx Parallel III Parallel IV cables. -
Page 11: Using The Smt351
Version 1.1 Page 11 of 24 SMT351 User Manual Using the SMT351 The SMT351 will normally store up to 1 GB of data in memory. It’s possible to change this setting using the SMT351_Capture function. Following are described the main features that user should keep in mind when using... -
Page 12: Fpga Configuration
1. Use the on-board JTAG header and Xilinx JTAG programming tools. 2. Send the configuration bitstream down the comport selected by SW1. The Sundance library for the SMT351 includes a function to configure the FPGA in this way. The table below gives the possible settings for SW1: Table 2: configuration comport selection. -
Page 13: Reset
FPGA without having to drive the TIM Global Reset signal. CONFIG falling will reset the SMT351 in the same way that a TIM global Reset pulse will. Other modules in the system that are sensitive to the TIM global Reset signal will not be affected by CONFIG. -
Page 14: Functional Description
Version 1.1 Page 14 of 24 SMT351 User Manual Functional description FPGA design overview The following diagram shows the data path of SMT351: Control Registers words port Memory bank 0 MBytes/ MBytes/ Memory bank 1 Figure 2: SMT351 FPGA data flow. -
Page 15: Sundance High Speed Bus (Shb)
SHB A is a receiver-only interface and SHB B is a transmitter-only interface; both are clocked at 100 MHz, giving a maximum data rate of 400 MB/s. Registers Command words can be sent over comport 3 to control the SMT351. Words received will be written into registers in the FPGA. See Register definition section for more details. -
Page 16: Clock Structure
Version 1.1 Page 16 of 24 SMT351 User Manual Clock structure This section describes the various clock domains in the FPGA. The figure below shows the four clock domains of the SMT351 design and their interrelation. Control Registers words port... -
Page 17: Fpga Implementation
Version 1.1 Page 17 of 24 SMT351 User Manual FPGA implementation This section gives some technical details about the FPGA firmware. Language Sundance uses Aldec Active-HDL tool for the design entry and the simulation. The FPGA is fully designed in VHDL. -
Page 18: Register Definition
Writing ‘1’ to this register will reset both input and output SHBs. RDBKEN Read back enable. When this bit is set read back of memory is enabled and SMT351 starts outputting data. STARTACQ When this bit is set to 1, data coming from SHB A are stored in DDR SDRAM. -
Page 19: Software
Software SMT351 comes with a software package that provides basic functions for using the board. The library is called Smt351.lib. SMT351_Config Definition Load a bitstream into the SMT351’s FPGA. Prototype void SMT351_Config (int Cp, const char *Bitstream) Parameters Cp: Number of the comport used to configure the SMT351... -
Page 20: Connector Locations
Version 1.1 Page 20 of 24 SMT351 User Manual Connector Locations Figure 5: SMT351 connector locations... -
Page 21: Jp2 Pinout
Version 1.1 Page 21 of 24 SMT351 User Manual JP2 pinout The following diagram shows JP2’s pinout:... -
Page 22: Figure 6: Ttl I/Os (Jp2) Pinout
Version 1.1 Page 22 of 24 SMT351 User Manual Figure 6: TTL I/Os (JP2) pinout The following table shows JP2 mapping to the FPGA: Signal name FPGA pin number TTL0 AC10 TTL1 AD10 TTL2 AC11 TTL3 AD11... -
Page 23: Jp1 Pinout
JP1 pinout Figure 7: JTAG header (JP1) pinout Pin number Description 3.3 Volts Ground... -
Page 24: Physical Properties
Version 1.1 Page 24 of 24 SMT351 User Manual Physical Properties Dimensions Weight Supply Voltages Supply Current +12V +3.3V -12V MTBF...
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