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Version 1.1.1
And totally independent read and write ports eliminate the need for high-speed bus
turn around. The memory is expected to be clocked at 166 MHz allowing a data
throughput rate of 1.3 GBytes/s.
The memory bank of the SMT398 is composed of 2 devices added in parallel in width
expansion architecture. The address bus, input clocks, R# and W# are common to
both devices. The data buses are not common.
Each chip is available in 3 different sizes (up to 164Mbits chips are expected)
QDR part number
CY7C1302V25
k7q1636(18)52a
k7q3236(18)52m.pdf
Table 3: QDR RAM sizes
Due to a board layout issue the total available QDR RAM is 2 Mbytes or 4Mbytes
with the 32Mb chips fitted.
QQ[36:0]
QD[36:0]
QSA[21:0]
QWn/QRn
QC/QCn (input)
QK/QKn (output)
R = 50 Ohms
V
= V
T
Figure 7:SMT398 QDR Width expansion arrangement.
Page 22 of 38
Size in
Size in
bits
Bytes
8Mb
1MBytes
16Mb
2MBytes
32Mb
4MBytes
QDR1
D
18
36
36
20
REF/2
Actual
Amount
Memory
of
size
memory
per board
512kx18
2 MBytes
1Mx18
4 MBytes
2Mx18
4 MBytes
QDR2
Q
D
18
18
2
2
SMT398 User Manual
V
=
TERM
R = 50 Ohms
Q
18
V
REF/2
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