Table Of Figures; Table Of Tables - Sundance Spas SMT398 User Manual

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Version 1.1.1
Page 5 of 38
SMT398 User Manual

Table of Figures

Figure 1:SMT398 Block Diagram .............................................................................................7
Figure 2: FPGA configuration in SelectMap mode using CPLD.............................................11
Figure 3: ComPort word Byte order........................................................................................12
Figure 4: V II Configuration Bitstream Word Format ..............................................................15
Figure 5: JTAG Chain on the SMT398 ...................................................................................18
Figure 6:SMT398 ZBT Memory Banks arrangement .............................................................21
Figure 7:SMT398 QDR Width expansion arrangement..........................................................22
Figure 8:SMT398 ComPorts connections ..............................................................................23
Figure 9: DC/DC converter dimensions (in inches) ................................................................28
Figure 10:SMT398 Components placement-Top view ...........................................................32
Figure 11: SMT398 Components placement-Bottom view.....................................................33
Figure 12: Top View QSH 30 .................................................................................................34
Figure 13: Top View of JTAG/Multilinx headers .....................................................................36

Table of Tables

Table 1: FPGA Choices..........................................................................................................16
Table 2: ZBTRAM sizes .........................................................................................................20
Table 3: QDR RAM sizes .......................................................................................................22
Table 4: External clock specification ......................................................................................26
Table 5: powering the devices................................................................................................27
Table 6: Virtex II, ZBT/QDR combinations in FULL configuration ..........................................30
Table 7: Virtex II, ZBT combinations in BASIC configuration .................................................31
Table 8: SHB interfaces table.................................................................................................35
Table 9: Connector J13-JTAG Header...................................................................................36
Table 10: Connector J13-Flying Lead Set #1.........................................................................37

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