Configuring With Multilinx; Fpga Readback And Partial Reconfiguration - Sundance Spas SMT398 User Manual

Version 1.1.1 Page 19 of 38 SMT398 User Manual

Configuring with MultiLINX

The Mutilinx cable can be used to configure the FPGA via JTAG or SelectMap mode.
See board header pinout in Table 9: Connector J13-JTAG Header, Table 10:
Connector J13-Flying Lead Set #1 and Table 11: Connector J12 Flying Lead Sets
3&4.
The MultiLINX cable set is a peripheral hardware product from Xilinx.
For additional information on the MultiLINX cable set, go to the following site:
Xilinx MultiLINX cable

FPGA Readback and Partial reconfiguration

Using Comm-port3
Readback and partial reconfiguration are enabled by a specific design for the CPLD,
not provided as a standard feature of the CPLD but that can be purchased from
Sundance. Contrary to the original design, the CPLD is dedicated to control the
FPGA and does not provide a communication channel to user logic residing on the
FPGA anymore. The CPLD is connected to ComPort number 3 of the SMT398
connector, which cannot be used anymore by the FPGA to transfer data.
Therefore, the CPLD controller can configure, readback, partially reconfigure the
Virtex II and capture.
Using MultiLINX /Parallel cable III or IV
The JTAG and the MultiLINX SelectMAP headers are also provided to enable
application debugging via suitable software. Typically, this will be Xilinx ChipScope
ILA (Integrated Logic Analyzer).
The ChipScope Analyzer supports both the Xilinx MultiLINX™ and Parallel Cable III
download cables for communication between the PC and FPGA(s). The MultiLINX
cable supports both USB (Windows 98 and Windows 2000) and RS-232 serial
communication from the PC. The Parallel Cable III supports only parallel port
communication from the PC to the Boundary Scan chain.