Mcecc Dram Size (S6) - Motorola MVME162P2 Series Installation And Use Manual

MCECC DRAM Size (S6)

MVME1X2P2 boards use SDRAM (Synchronous DRAM) in place of
DRAM. The MVME162P2's 16/32MB synchronous SDRAM is
configurable to emulate either of the following memory models:
The two memory controllers modeled in the Petra ASIC duplicate the
functionality of the "parity memory controller" found in MC2 ASICs as
well as that of the "single-bit error correcting/double-bit error detecting"
memory controller found in MCECC ASICs. Board firmware will
initialize the memory controller as appropriate.
If the Petra ASIC is supporting MVME1X2P4 functionality, firmware will
enable the parity (MC2) memory controller model. If the Petra ASIC is
supporting MVME1X2P2 functionality, firmware will enable either the
parity or the MCECC memory controller model, depending on the board
configuration. Board configuration is a function of switch settings and
resistor population options.
S6 comes into play in the MCECC memory controller model. S6 is a four-
segment slide switch whose lower three segments establish the size of the
ECC DRAM (segment 4 is not used.) Refer to the illustration and table
below for specifics.
http://www.motorola.com/computer/literature
1MB, 4MB, 8MB, or 16MB shared parity-protected DRAM
4MB, 8MB, 16MB, or 32MB ECC-protected DRAM
S6
ON
4
1
Preparing the Board
OFF
16MB MCECC DRAM
(factory configuration )
2737 0004
1
1-21