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4-3-4 Input signal status flag (Response byte 3)
Byte3 at Response is the status area of the external input signal from the interface connector, (X4).
Byte
bit 7
SI-MON5
3
/E-STOP
(*) Other than above, CS_Complete can be allocated to either bit.
• On MINAS-A5N, 8 external input connection terminals are provided to which functions and logics may be assigned
individually. For details, refer to Technical Reference, SX-DSV02309"Section 2-4-1", Functional Specification.
• When function is not assigned to a terminal, corresponding bit in this status flag is set to 0.
A terminal can be assigned with 2 or more functions, but only 1 per control mode. However, this is confusion because
some functions are enabled and some are disabled upon changing control modes: Ideally, functions allocated to a
terminal should be common to all control modes.
• Because the following pair of designations is assigned to the same bit position, only one of designations can be
selected: SI-MON1/EXT1, SI-MON2/EXT2, SI-MON3/EXT3, SI-MON4/EX-SON and SI-MON5/E-STOP. If
attempt is made to allocate 2 or more functions to the same bit, Err.33.0 (I/F input multiple allocation error 1 protect)
or Err.33.1 (I/F input multiple allocation error 2 protect) will be enabled.
• This status returns the logical status (1: function active) but not physical status (input transistor ON/OFF state).
However, status of driver inhibit input (POT/NOT) can be logically set.
• EXT1, EXT2 and EXT3 indicate the state of input signal but not complete state of latch.
• For driver inhibit input (POT/NOT), status response condition, status bit arrangement and status logic can be set as
shown below while the function is disabled (Pr.5.04 = 1), through the parameter Pr.7.23 (RTEX function extended
setup 2).
Because CCWL and CWL used on MINAS-A4N series are changed to POT and NOT, respectively, on MINAS-A5N
series, correctly set this parameter and Pr.0.00 (Movement direction setting) Rotating direction setup to make the
functions effective on MINAS-A4N.
Class
No. Attribute
7
23
• Noise filtering process is performed when capturing the input signals within the servo driver, and this causes some
detection delay. Total delay time including the transmission delay in communication will be several ms. If this delay
time gives inconvenience, provide the system that directly connects the sensor signal to host controller.
R2.0
bit 6
bit 5
SI-MON3
SI-MON4
/EXT3
/EX-SON
/CS3
Title
Range
RTEX function
-32768
B
extended setup 2
–32767
bit 4
bit 3
SI-MON2
SI-MON1
/EXT2
/EXT1
/CS2
/CS1
Unit
[bit 2] Set RTEX status response condition when POT/NOT
function is disabled Pr.5.04 = 1.
0: Enable in terms of RTEX status (response)
1: Disable in terms of RTEX status (not response =
normally 0)
[bit 3] POT/NOT RTEX status bit arrangement set up
0: POT at bit 1; NOT at bit 0
–
1: NOT at bit 1; POT at bit 0
[bit 6] POT/NOT RTEX status logic set up
0: No inversion (active 1)
1: Inversion (active 0)
▪ For description on other bits, refer to Technical reference,
SX-DSV02309"Section 9-1", Functional Specification.
Motor Business Division, Appliances Company, Panasonic Corporation
No. SX-DSV02310 - 40 -
bit 2
bit 1
POT
HOME
/NOT
Description
bit 0
NOT
/POT
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