Siemens SIMATIC ET 200iS Manual page 9

7-9 Interrupts from Analog Input Modules.............................................................7-27
7-10 Structure of the Slave Diagnostic Information.................................................7-29
7-11 Structure of the ID-Related Diagnostic Information for the ET 200iS .............7-33
7-12 Module Status .................................................................................................7-34
7-13 Structure of the Channel-Related Diagnostic Information ..............................7-36
7-14 Structure of the Interrupt Status of the Interrupt Section ................................7-39
7-15 Structure of Bytes x+4 to x+7 for Diagnostic Interrupts ..................................7-40
7-16 Structure Starting at Byte x+8 for Diagnostic Interrupts
(Input or OutputModules) ................................................................................7-41
7-17 Example of a Diagnostic Interrupt ...................................................................7-42
7-18 Example of a Diagnostic Interrupt (continued)................................................7-43
7-19 Structure Starting at Byte x+4 for Hardware Interrupts (Analog Input) ...........7-44
7-20 Structure Starting at Byte x+4 for Remove/Insert Interrupts ...........................7-44
7-21 Structure Starting at Byte x+4 for Update Interrupt.........................................7-45
8-1 Automatic Parameter Assignment after Replacing a Module ...........................8-3
9-1 Mark for Australia ..............................................................................................9-2
10-1 Block Diagram of the Terminal Module TM-PS...............................................10-3
10-2 Block Diagram of the Terminal Module TM-IM ...............................................10-5
10-3 Block Diagram of the Terminal Module TM-E30S44-iS / E30C44-iS..............10-7
11-1 Block Diagram of the Power Supply Module...................................................11-1
12-1 Block Diagram of the IM 151-2........................................................................12-2
12-2 Example of Time Stamping and Edge Evaluation...........................................12-6
13-1 Block Diagram of the 4DI NAMUR ..................................................................13-4
13-2 Block Diagram of the 2DO DC25V/25mA .......................................................13-8
13-3 Output Curve .................................................................................................13-11
13-4 Principle of Pulse Extension..........................................................................13-14
13-5 Principle Behind Flutter Monitoring ...............................................................13-16
14-1 Compensation by 2AI RTD ...........................................................................14-40
14-2 Example of Parameter Assignment for Reference Junctions .......................14-41
14-3 Block Diagram of the 2AI I 2WIRE................................................................14-46
14-4 Block Diagram of the 2AI I 4WIRE................................................................14-50
14-5 Block Diagram of the 2AI RTD ......................................................................14-54
14-6 Block Diagram of the 2AI TC.........................................................................14-58
14-7 Block Diagram of the 2AO I...........................................................................14-62
14-8 Example of the Influence of Smoothing on the Step Response ...................14-70
15-1 The HART Signal ............................................................................................15-2
15-2 Location of the HART Analog Modules in the Distributed System .................15-4
15-3 System Environment for Using HART.............................................................15-5
15-4 Block Diagram of the 2AI I 2WIRE HART .......................................................15-9
15-5 Block Diagram of the 2AI I 4WIRE HART .....................................................15-14
15-6 Block Diagram of the 2AO I HART................................................................15-19
17-1 Terminal Module TM-PS with Power Supply Module PS Inserted..................17-1
17-2 Terminal Module TM-IM with Interface Module IM 151-2 Inserted .................17-2
17-3 Terminal Module TM-E with Electronics Module Inserted ..............................17-2
17-4 Bus Termination Module .................................................................................17-3
18-1 Reaction Times between the DP Master and ET 200iS .................................18-1
18-2 Calculating the Reaction Time ........................................................................18-2
18-3 Example of Calculating the ET 200iS Reaction Time .....................................18-3
18-4 Cycle Times of the Analog Input Channel.......................................................18-4
18-5 Cycle Time of the Analog Output Module .......................................................18-5
18-6 Response Time of an Analog Output Channel ...............................................18-6
19-1 Address Space of Digital Input Modules .........................................................19-1
19-2 Address Space of Digital Output Modules ......................................................19-1
ET 200iS Distributed I/O Station
A5E00087831-02
Contents
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