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TMP96C141AF
7
6
5
←
TRUN
–
x
–
←
P8CR
–
–
–
INTET54 ←
1
1
0
←
T4FFCR
1
1
0
←
T4MOD
0
0
1
←
TREG5
*
*
*
←
TRUN
1
x
–
Note:
When used as an event counter, set the prescaler in RUN mode.
(3)
16-bit Programmable Pulse Generation (PPG) Output
Mode
Since both timers operate in exactly the same way,
timer 4 is used for the purposes of explanation.
The PPG mode is obtained by inversion of the timer
7
6
5
←
TRUN
–
x
–
←
TREG4
*
*
*
←
TREG5
*
*
*
←
T45CR
0
x
x
←
T4FFCR
1
1
0
←
T4MOD
0
0
1
←
P8CR
–
–
–
←
P8FC
x
–
x
←
TRUN
1
x
–
Note:
x; don't care
–; no change
Figure 3.9 (11). Programmable Pulse Generation (PPG) Output Waveforms
96
4
3
2
1
0
0
–
–
–
–
–
–
–
–
0
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
*
*
*
*
*
1
–
–
–
–
4
3
2
1
0
0
–
–
–
–
*
*
*
*
*
*
*
*
*
*
x
–
–
–
1
0
1
1
0
0
0
0
1
*
*
(** = 01, 10, 11)
–
–
1
–
–
x
–
1
x
x
1
–
–
–
–
Stop timer 4.
Set P80 to input mode.
Enable INTTR5 and sets interrupt level 4, while
disables INTTR4.
Disable trigger.
Select TI4 as the input clock.
Set the number of counts (16 bits).
Start timer 4.
flip-flop TFF4 that is to be enabled by the match of the
up-counter UC4 with the timer register TREG4 or 5
and to be output to TO4 (also used as P82). In this
mode, the following conditions must be satisfied.
(Set value of TREG4) < (Set value of TREG5)
Stop timer 4.
Set the duty (16 bits).
Set the cycle (16 bits).
Double buffer of TREG4 enable.
(Changes the duty and cycle at the interrupt INTTR5)
Set the mode to invert TFF4 at the match with
TREG4/TREG5, and also sets TFF4 to "0".
Select internal clock for input and disables the capture function.
)
Assign P82 as TO4.
Start timer 4.
TOSHIBA CORPORATION
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