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The serial channel has a buffer register for transmitting
and receiving operations, in order to temporarily store trans-
mitted or received data, so that transmitting and receiving
operations can be done independently (full duplex).
However, in I/O interface mode, SCLK (serial clock) pin is
used for both transmission and receiving, the channel
becomes half-duplex.
The receiving data register is of a double buffer structure
to prevent the occurrence of overrun error and provides one
frame of margin before CPU reads the received data. The
receiving data register stores the already received data while
the buffer register receives the next frame data.
By using CTS and RTS (there is no RTS pin, so any one
port must be controlled by software), it is possible to halt data
send until CPU finishes reading receive data every time a frame
is received (Handshake function).
In the UART mode, a check function is added not to start
the receiving operation by error start bits due to noise. The
channel starts receiving data only when the start bit is
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detected to be normal at least twice in three samplings.
When the transmission buffer becomes empty and
requests the CPU to send the next transmission data, or when
data is stored in the receiving data register and the CPU is
requested to read the data, INTTX or INTRX interrupt occurs.
Besides, if an overrun error, parity error, or framing error occurs
during receiving operation, flag SC0CR/SC1CR <OERR,
PERR, FERR> will be set.
The serial channel 0/1 includes a special baud rate gen-
erator, which can set any baud rate by dividing the frequency
of four clocks ( φ T0, φ T2, φ T8, and φ T32) from the internal pres-
caler (shared by 8-bit/16-bit timer) by the value 2 to 16.
In I/O interface mode, it is possible to input synchronous
signals as well as to transmit or receive data by external clock.
3.11.1 Control Registers
The serial channel is controlled by three control registers
SC0CR, SC0MOD, and BR0CR. Transmitted and received
data is stored in register SC0BUF.
TMP96C141AF
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