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The initialization for 4-phase 1-2 step excitation is as
follows:
By rearranging the initial value "b7 b6 b5 b4 b3 b2
b1 b0" to "b7 b3 b6 b2 b5 b1 b4 b0", the consecutive 3
bits are set to "1" and other bits are set to "0" (positive
logic).
For example, if b7, b3, and b6 are set to "1", the ini-
tial value becomes "11001000", obtaining the output
waveforms as shown in Figure 3.10 (11).
To get an output waveform of negative logic, set val-
ues 1s and 0's of the initial value should be inverted. For
Figure 3.10 (12). Block Diagram of 4-Phase 1-2 Step Excitation (Normal Rotation)
TOSHIBA CORPORATION
example, to change the output waveform shown in Fig-
ure 3.10 (11) into negative logic, change the initial value
to "00110111".
The operation will be explained below for channel 0.
The output latch of PG0 (shared by P6) and the
shifter alternate register (SA0) for Pattern Generation are
shifted at the rising edge of trigger signal from the timer
to be output to the port. The direction of shift is set by
PG01CR <CCW0>.
Figure 3.10 (12) shows the block diagram.
TMP96C141AF
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