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TMP96C141AF
The watchdog timer is a 22-stage binary counter which
uses φ (fc/2) as the input clock. There are four outputs from the
16
18
binary counter: 2
/fc, 2
of the outputs with the WDMOD register generates a watch-
dog interrupt, and outputs watchdog timer out when an over-
flow occurs.
Since the watchdog timer out pin (WDTOUT) outputs "0"
due to a watchdog timer overflow, the peripheral devices can
146
20
22
/fc, 2
/fc, and 2
/fc. Selecting one
Figure 3.13 (2). Normal Mode
Figure 3.13 (3). Reset Mode
be reset. The watchdog timer out pin is set to 1 by clearing the
watchdog timer (by writing a clear code 4EH in the WDCR reg-
ister). In other words, the WDTOUT keeps outputting "0" until
the clear code is written.
The watchdog timer out pin can also be connected to the
reset pin internally. In this case, the watchdog timer out pin
(WDTOUT) outputs 0 at 8 to 20 states (800ns to 2 µ s @
20MHz) and resets itself.
TOSHIBA CORPORATION
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