Toshiba TMP96C141AF Manual page 14

TMP96C141AF
The following timing chart is a high-speed µ DMA cycle of
the Transfer Address Increment mode (the other mode exe-
(2) Register Configuration (CPU Control Register)
These Control Registers cannot be set only "LCD cr, r" instruction.
14
cept the Read-only mode is same as this)
(Condition: MIN mode, 16bit Bus width for 16M Byte, 0 wait)
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