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Timer Control (3/4)
Symbol
Name
Address
16bit Timer 4
Flip-flop
T4FFCR
Control
T45CR
T4, T5 Control
16bit Timer
TREG6L
(Prohibit
Register 6L
RMW)
16bit Timer
TREG6H
(Prohibit
Register 6H
RMW)
16bit Timer
TREG7L
(Prohibit
Register 7L
RMW)
16bit Timer
TREG7H
(Prohibit
Register 7H
RMW)
Capture
CAP3L
Register 3L
Capture
CAP3H
Register 3H
Capture
CAP4L
Register 4L
Capture
CAP4H
Register 4H
16bit Timer 5
T5MOD
Source
CLK and
MODE
TOSHIBA CORPORATION
7
6
TFF5C1
TFF5C0
W
0
0
39H
00 : Invert TFF5
01 : Set TFF5
10 : Clear TFF5
11 : Don't care
–
R/W
0
3AH
Fix at "0"
40H
41H
42H
43H
44H
45H
46H
47H
0
0
48H
5
4
CAP2T4
CAP1T4
R/W
0
0
TFF4 Invert Trigger
0 : Trigger Disable
1 : Trigger Enable
PG1 shift
trigger
0 : Timer 0, 1
1 : Timer 5
–
W
Undefined
–
W
Undefined
–
W
Undefined
–
W
Undefined
–
R
Undefined
–
R
Undefined
–
R
Undefined
–
R
Undefined
CAP3IN
CAP34M1
CAP34M0
R/W
0
0
Capture Timing
0 : Soft-
00 : Disable
01 : T16 ↑ T17 ↑
Capture
10 : T16 ↑ T16 ↓
1 : Don't care
11 : TFF1 ↑ TFF1 ↓
TMP96C141AF
3
2
1
EQ5T4
EQ4T4
TFF4C1
0
0
0
00 : Invert TFF4
01 : Set TFF4
10 : Clear TFF4
11 : Don't care
PG1T
PG0T
DB6EN
R/W
0
0
0
PG0 shift
trigger
O : Timer 0, 1
1 : Timer 4
CLE
T5CLK1
0
0
0
1 : UC5
00 : Invert TFF6
Clear
01 : Set TFF6
Enable
10 : Clear TFF6
11 : Don't care
0
TFF4C0
W
0
Source Clock
DB4EN
0
1 : Double
Buffer
Enable
T5CLK0
W
0
Source Clock
167
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