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TMP96C141AF
When the double buffer of TREG0 is enabled in this
mode, the value of register buffer will be shifted in TREG0 each
time TREG1 matches UC0.
Example: Generating 1/4 duty 50KHz pulse @ fc = 16MHz)
• Calculate the value to be set for timer register.
To obtain the frequency 50KHz, the pulse cycle t
should be: t = 1/50KHz = 20µs.
Given φ T1 = 0.5µs @ 16MHz),
20µs ÷ 0.5µs = 40
Consequently, to set the timer register 1 (TREG1) to
7
6
←
TRUN
–
x
←
TMOD
1
0
←
TREG0
0
0
←
TREG1
0
0
←
TFFCR
–
–
←
P7CR
x
x
←
P7FC
x
x
←
TRUN
1
x
Note : x; don't care
–; no change
66
Figure 3.7 (12). Operation of Register Buffer
5
4
3
2
1
0
–
–
–
–
0
0
x
x
x
x
0
1
0
0
1
0
1
0
1
0
1
0
0
0
–
1
0
1
1
x
x
x
–
–
1
–
x
x
–
–
1
x
–
–
–
–
1
1
Use of the double buffer makes easy handling of low duty
waves (when duty is varied).
TREG1 = 40 = 28H and then duty to 1/4, t x 1/4 =
20µs x 1/4 = 5µs
Therefore, set timer register 0 (TREG0) to TREG0 = 10
= 0AH.
Stop timer 0, and clear it to "0".
Set the 8-bit PPG mode, and select φ T1 as input clock.
Write "0AH".
Write "28H".
Sets TFF1 and enables the inversion and double buffer enable.
Writing "10" provides negative logic pulse.
)
Set P71 as TO1 pin.
Start timer 0 and timer 1 counting.
5µs ÷ 0.5µs = 10
TOSHIBA CORPORATION
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