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MSB
7
6
←
TRUN
-
x
←
TMOD
1
1
←
TREG0
0
1
←
TFFCR
x
x
←
P7CR
x
x
←
P7FC
x
x
←
TRUN
1
x
Note:
x; don't care
–; no change
φ T1
6
2
-1
31.5µsec (31.7kHz)
7
2
-1
63.5µsec (15.7kHz)
8
2
-1
127µsec
(7.8kHz)
(5)
Table 3.7 (4) shows the list of 8-bit timer modes.
Register Name
Name of Function in
Function
16-bit timer mode
8-bit timer x 2 channels
8-bit PPG x 1 channel
8-bit PWM x 1 channel
8-bit timer x 1 channel
Note:
–: don't care
TOSHIBA CORPORATION
LSB
5
4
3
2
1
0
–
–
–
–
–
0
1
0
–
–
0
1
0
0
1
0
0
0
x
x
1
0
1
x
x
x
–
–
1
–
x
x
–
–
1
x
–
–
–
–
–
1
Table 3.7 (3) PWM Cycle and the Setting of 2
PWM Cycle (@ fc =16MHz)
φ T4
126msec (7.9kHz)
254msec (3.9kHz)
510msec (1.9kHz)
Table 3.7 (4) Timer Mode Setting Registers
T10M
Timer Mode
01
00
10
11
11
Stop timer 0, and clear it to "0".
Set 8-bit PWM mode (cycle: 2
Write "48H".
Clears TFF1, enables the inversion and double buffer.
)
Set P71 as the TO1 pin.
Start timer 0 counting.
φ T16
φ T1
0.50µsec (1.9kHz)
25.2µsec (39.0kHz)
1.01µsec (0.98kHz)
50.8µsec (19.7kHz)
2.04µsec (0.49kHz)
102µsec
TMOD
PWMM
T1CLK
Upper Timer
PWM0 Cycle
Input Clock
–
Lower timer match :
φ T1, φ T16, φ T256
–
(00, 01, 10, 11)
–
6
7
8
2
- 1, 2
- 1, 2
- 1
(01, 10, 11)
φ T1, φ T16, φ T256
–
(01, 10, 11)
- 1) and select φ T1 as the input clock.
7
n
-1 Counter
PWM Cycle (@ fc = 20 MHz)
φ T4
100µsec (10.0kHz)
203µsec (4.9kHz)
(9.80kHz)
408µsec (2.4kHz)
T0CLK
Lower Timer
Input Clock
External clock,
φ T1, φ T4, φ T16
–
(00, 01, 10, 11)
External clock,
φ T1, φ T4, φ T16
(00, 01, 10, 11)
External clock,
φ T1, φ T4, φ T16
–
(00, 01, 10, 11)
External clock,
φ T1, φ T4, φ T16
–
(00, 01, 10, 11)
–
TMP96C141AF
φ T16
0.40msec (2.4kHz)
0.81msec (1.2kHz)
1.63msec (0.61kHz)
TFFCR
TFF1IS
Timer F/F Invert
Signal Select
–
0 : Lower timer output
1 : Upper timer output
–
–
Output disabled
69
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