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3.3.1 General-Purpose Interrupt Processing
When accepting an interrupt, the CPU operates as follows:
(1) The CPU reads the interrupt vector from the interrupt
controller. When more than one interrupt with the same
level is generated simultaneously, the interrupt controller
generates interrupt vectors in accordance with the
default priority (which is fixed as follows: the smaller the
vector value, the higher the priority), then clears the inter-
rupt request.
(2) The CPU pushes the program counter and the status
register to the system stack area (area indicated by the
system mode stack pointer).
(3) The CPU sets a value in the CPU interrupt mask register
<IFF2 to 0> that is higher by 1 than the value of the
accepted interrupt level. However, if the value is 7, 7 is
set without an increment.
(4) The CPU sets the <SYSM> flag of the status register to 1
and enters the system mode.
(5) The CPU jumps to address 8000H + interrupt vector,
then starts the interrupt processing routine.
In minimum mode, all the above processing is completed
(1.5 µ s @ 20MHz). In maximum mode, it is com-
in
15 states
pleted in 17 states.
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Bus Width of Stack
Interrupt Processing State Number
Area
MAX mode
8 bit
16 bit
To return to the main routine after completion of the inter-
rupt processing, the RETI instruction is usually used. Executing
this instruction restores the contents of the program counter
and the status registers.
Though acceptance of non-maskable interrupts cannot
be disabled by program, acceptance of maskable interrupts
can. A priority can be set for each source of maskable inter-
rupts. The CPU accepts an interrupt request with a priority
higher than the value in the CPU mask register <IFF2 to 0>.
The CPU mask register <IFF2 to 0> is set to a value higher by
1 than the priority of the accepted interrupt. Thus, if an inter-
rupt with a level higher than the interrupt being processed is
generated, the CPU accepts the interrupt with the higher level,
causing interrupt processing to nest. The CPU does not
accept an interrupt request of the same level as that of the
interrupt being processed.
Resetting initializes the CPU mask registers <IFF2 to 0>
to 7; therefore, maskable interrupts are disabled.
The addresses 008000H to 0081FFH (512 bytes) of the
TLCS-900 are assigned for interrupt processing entry area.
TMP96C141AF
Min mode
23
19
17
15
11
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