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3.13.2 Control Registers
Watchdog timer WDT is controlled by two control registers
WDMOD and WDCR.
(1)
Watchdog Timer Mode Register (WDMOD)
Setting the detecting time of watchdog timer
<WDTP>
This 2-bit register is used to set the watchdog timer
interrupt time for detecting the runaway. This register is
initialized to WDMOD <WDTP1, 0> = 00 when reset,
16
and therefore 2
/fc is set. (The number of states is
approximately 32,768).
Watchdog timer enable/disable control register
<WDTE>
When reset, WDMOD <WDTE> is initialized to "1"
enable the watchdog timer.
• Disable control
←
WDMOD
0
–
←
WDCR
1
0
• Enable control
Set WDMOD <WDTE> to "1".
• Watchdog timer clear control
The binary counter can be cleared and resume
←
WDCR
0
1
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–
–
–
–
x
x
1
1
0
0
0
1
0
0
1
1
1
0
To disable, it is necessary to clear this bit to "0" and
write the disable code (B1H) in the watchdog timer
control register WDCR. This makes it difficult for the
watchdog timer to be disabled by runaway.
However, it is possible to return from the disable state
to enable state by merely setting <WDTE> to "1".
Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the
watchdog timer with RESET terminal, internally. Since
WDMOD <RESCR> is initialized to 0 at reset, a reset
by the watchdog timer will not be performed.
(2)
Watchdog Timer Control Register (WDCR)
This register is used to disable and clear the binary
counter of the watchdog timer function.
Clear WDMOD <WDTE> to "0".
Write the disable code (B1H).
counting by writing clear code (4EH) into the WDCR reg-
ister.
Write the clear code (4EH).
TMP96C141AF
147
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