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3.6.2 Chip Select Image
An image of the actual chip select is shown below. Out of the
whole memory area, address areas that can be specified are
divided into four parts. Addresses from 000000H to 3FFFFFH
are divided differently: 7F00H to 7FFFH is specified for CS0;
480H to 7FFFH, for CS1; and 8000H to 3FFFFFH, for CS2.
The reason is that a device other than ROM (i.e., RAM or I/O)
might be connected externally.
The addresses 7F00 to 7FFFH (256 bytes) for CS0 are
mapped mainly for possible expansions to external I/O.
The addresses 480H to 7FFFH (approximately 31K
Supplement 1:
Access priority is highest for built-in I/O, then built-in memory, and lowest for the chip select/wait controller.
Supplement 2:
External areas other than CS0 to CS2 are accessed in 16-bit data bus (0 wait) mode.
When using the chip select/wait controller, do not specify the same address area more than once. (However, when addresses 7F00H - 7FFFH
for CS0 and 480H - 7FFFH for CS1 are specified, in other words, specifications overlap, only the CS0 setting/pin is active.)
TOSHIBA CORPORATION
CS0
000000H
7F00H
8000H
B0C1, 0 = "00"
400000H
800000H
B0C1, 0 = "01"
C00000H
B0C1, 0 = "10"
FFFFFFH
B0C1, 0 = "11"
(Mainly for I/O)
bytes) for CS1 are mapped there mainly for possible exten-
sions to external RAM.
The addresses 8000H to 3FFFFFFH (approximately
4Mbytes) for CS2 are mapped mainly for possible extensions
to external ROM. After reset, CS2 is enabled in 16-bit bus and
2-wait. With the TMP96C141AF, which does not have a built-
in ROM, the program is externally read at address 8000H in
this setting (16-bit bus, 2-wait). With the TMP96CM40F/
TMP96PM40F, which has a built-in ROM, addresses from
8000H to FFFFFH are used as the internal ROM area; CS2 is
disabled in this area. After reset, the CPU reads the program
from the built-in ROM in 16-bit bus, 0-wait mode.
CS1
B1C1, 0 = "00"
B2C1, 0 = "00"
B1C1, 0 = "01"
B2C1, 0 = "01"
B1C1, 0 = "10"
B2C1, 0 = "10"
B1C1, 0 = "11"
B2C1, 0 = "11"
(Mainly for RAM)
(Mainly for ROM)
TMP96C141AF
CS2
51
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