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TMP96C141AF
Timer Control (2/4)
Symbol
Name
Address
PWM
PFFCR
Flip-flop
Control
16-bit Timer
(Prohibit
TREG4L
Register 4L
RMW)
16-bit Timer
(Prohibit
TREG4H
Register 4H
RMW)
16-bit Timer
(Prohibit
TREG5L
Register 5L
RMW)
16-bit Timer
(Prohibit
TREG5H
Register 5H
RMW)
Capture
CAP1L
Register 1L
Capture
CAP1H
Register 1H
Capture
CAP2L
Register 2L
Capture
CAP2H
Register 2H
16-bit Timer 4
T4MOD
Source
CLK and
MODE
166
7
6
FF3C1
FF3C0
W
0
0
00 : Don't care
2AH
01 : Set TFF3
10 : Clear TFF3
11 : Don't care
30H
31H
32H
33H
34H
35H
36H
37H
CAP2T5
EQ5T5
R/W
0
0
38H
TFF5 INV TRG
O: TRG Disable
1: TRG Enable
5
4
FF3TRG1
FF3TRG0
R/W
0
0
00 : Prohibit TFF3
Inverted
01 : Invert if matched
10 : Set if matched;
Clear if overflowed
11 : Clear if matched;
set if overflowed
–
W
Undefined
–
W
Undefined
–
W
Undefined
–
W
Undefined
–
R
Undefined
–
R
Undefined
–
R
Undefined
–
R
Undefined
CAP1IN
CAP12M1
CAP12M0
W
0
0
0 : Soft-
Capture Timing
Capture
00 : Disable
01 : T14 ↑ T15 ↑
1 : Don't care
10 : T14 ↑ T14 ↓
11 : TFF1 ↑ TFF1 ↓
3
2
1
FF2C1
FF2C0
FF2TRG1
W
0
0
0
00 : Don't care
00 : Prohibit TFF2
01 : Set TFF2
10 : Clear TFF2
01 : Invert if matched
11 : Don't care
10 : Set if matched;
11 : Clear if matched;
CLE
T4CLK1
R/W
0
0
0
1 : UC4
Source Clock
Clear
00 : TI4
01 : φ T1
Enable
10 : φ T4
11 : φ T16
TOSHIBA CORPORATION
0
FF2TRG0
R/W
0
Inverted
Clear if overflowed
set if overflowed
T4CLK0
0
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