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TMP96C141AF
2.2 Pin Names and Functions
The names of input/output pins and their functions are described below.
Number
Pin Name
of Pins
P00 ~ P07
8
AD0 ~ AD7
P10 ~ P17
AD8 ~ AD15
8
A8 ~ A15
P20 ~ P27
A0 ~ A7
8
A16 ~ A23
P30
1
RD
P31
1
WR
P32
1
HWR
P33
1
WAIT
P34
BUSRQ
1
P35
BUSAK
1
P36
1
R/W
P37
1
RAS
P40
CS0
1
CAS0
Note:
With the external DMA controller, this device's built-in memory or built-in I/O cannot be accessed using the BUSRQ and BUSAK pins.
4
Table 2.2. Pin Names and Functions
I/O
I/O
Port 0: I/O port that allows I/O to be selected on a bit basis
Tri-state
Address / data (lower): 0 - 7 for address / data bus
I/O
Port 1: I/O port that allows I/O to be selected on a bit basis
Tri-state
Address data (upper): 8 - 15 for address / data bus
Output
Address: 8 to 15 for address bus
I/O
Port 2: I/O port that allows selection of I/O on a bit basis (with pull-down resistor)
Output
Address: 0 - 7 for address bus
Output
Address: 16 - 23 for address bus
Output
Port 30: Output port
Output
Read: Strobe signal for reading external memory
Output
Port 31: Output port
Output
Write: Strobe signal for writing data on pins AD0 -7
I/O
Port 32: I/O port (with pull-up resistor)
Output
High write: Strobe signal for writing data on pins AD8 - 15
I/O
Port 33: I/O port (with pull-up resistor)
Input
Wait: Pin used to request CPU bus wait
Port 34: I/O port (with pull-up resistor)
I/O
Bus request: Signal used to request high impedance for AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0,
Input
CS1, and CS2 pins. (For external DMAC)
Port 35: I/O (with pull-up resistor)
I/O
Bus acknowledge: Signal indicating that AD0 - 15, A0 - 23, RD, WR, HWR, R/W, RAS, CS0, CS1, and CS2
Output
pins are at high impedance after receiving BUSRQ. (For external DMAC)
I/O
Port 36: I/O port (with pull-up resistor)
Output
Read/write: 1 represents read or dummy cycle; 0, write cycle.
I/O
Port 37: I/O port (with pull-up resistor)
Output
Row address strobe: Outputs RAS strobe for DRAM.
I/O
Port 40: I/O port (with pull-up resistor)
Output
Chip select 0: Outputs 0 when address is within specified address area.
Output
Column address strobe 0: Outputs CAS strobe for DRAM when address is within specified address area.
Functions
TOSHIBA CORPORATION
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