Xilinx VCU128 User Manual page 71

Table 26: XCVU37P U1 to QSFP28 Module Control and I2C Connections (cont'd)
FPGA (U1) Pin
U54.20
Notes:
1. The QSFP28 connector control signals are level-shifted.
2. The four QSFP28 connector I2C SCL/SDA signals are connected via I2C switch U54 to the I2C1_SCL/SDA bus. See
Bus, Topology, and Switches
For additional information about the quad small form factor pluggable (28 Gb/s QSFP28) module,
see the SFF-8663 and SFF-8679 specifications for the 28 Gb/s QSFP+ on the
Affiliates website.
10/100/1000 Mb/s Tri-speed Ethernet PHY
[Figure 2, callout 22]
The VCU128 evaluation board uses the TI PHY device DP83867ISRGZ (U62) for Ethernet
communications at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The board supports SGMII mode only.
The PHY connection to a user-provided Ethernet cable is through RJ-45 connector P2, a Wurth
7499111221A with built-in magnetics and status LEDs. On power-up, or on reset, the PHY is
configured to operate in SGMII mode with PHY address[4:0] = 00011. The following table lists
the FPGA U1 to U62 DP83867ISRGZ Ethernet PHY connections. This table also shows the net
names for the connections from the FPGA to the Ethernet PHY. ENET_SGMII_IN correlates with
the SGMII_TX ports in the FPGA design, and ENET_SGMII_OUT correlates with the SGMII_RX
ports.
Table 27: XCVC37P U1 to Ethernet PHY U62 Connections
FPGA
(U1) Pin
BG23
BN27
BF22 ENET_PDWN_B_I_INT_B_O
BH22
BG22
BJ21
BH21
BK22
BK23
U65.10
BP27
BJ23
UG1302 (v1.0) December 21, 2018
VCU128 Board User Guide
Schematic Net
1 2
Name ,
QSFP4_I2C_SCL
section
Net Name
ENET_MDIO
ENET_MDC
ENET_SGMII_IN_N
ENET_SGMII_IN_P
ENET_SGMII_OUT_N
ENET_SGMII_OUT_P
ENET_SGMII_CLK_N
ENET_SGMII_CLK_P
GEM3_ENET_RESET_B
ENET_COL_GPIO
ENET_CLKOUT
Chapter 3: Board Component Descriptions
FPGA (U1)
Module Pin Num
Direction
Output 11
I/O Standard
Pin
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
LVCMOS18
NA
LVCMOS18
LVCMOS18
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Module Pin Name
SCL
SNIA Technology
DP83867ISRGZ U62
Name
17 MDIO
16 MDC
44 INT_PWDN
28 TX_D1_SGMII_SIP
27 TX_D0_SGMII_SIN
36 RX_D3_SGMII_SON
35 RX_D2_SGMII_SOP
34 RX_D1_SGMII_CON
33 RX_D0_SGMII_COP
43 RESET_B
39 GPIO_2
18 CLK_OUT
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I2C
71