Xilinx VCU128 User Manual page 43

Programmable QSFP1 Clock
[Figure 2, callout 13]
The VCU128 evaluation board has a SI570 I2C programmable low-jitter 3.3V LVDS differential
oscillator (U95) connected to FPGA U1 GTY bank 135 MGTREFCLK0 P/N pins P42 and P43
(series capacitor coupled), respectively.
On power-up, the U95 SI570 user clock defaults to an output frequency of 156.250 MHz. The
Zynq-7000 SoC system controller or FPGA implemented user IP can change the output
frequency within the range of 10 MHz to 810 MHz through an I2C interface. Power cycling the
VCU128 evaluation board resets the QSFP1 clock to the default frequency of 156.250 MHz.
• Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz)
• Frequency tolerance: 50 ppm
• 3.3V LVDS differential output
The programmable QSFP1 clock circuit is shown in the following figure.
UG1302 (v1.0) December 21, 2018
VCU128 Board User Guide
Chapter 3: Board Component Descriptions
QSFP1 Clock
Figure 13:
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