Xilinx VCU128 User Manual page 41

QDR4 Interface Clock
[Figure 2, callout 12]
The VCU128 evaluation board has a SiTime 100 MHz fixed frequency low-jitter 3.3V LVDS
differential oscillator (U96) connected to FPGA U1 HP bank 69 QDR4 interface GC pins BJ4 (P)
and BK3 (N) and is series capacitor coupled.
• Fixed frequency oscillator: SiTime SIT9120AI-2D3-33E100.0000 (100 MHz)
• 0.6 ps RMS phase jitter (random) over 12 kHz to 20 MHz bandwidth
• 3.3V LVDS differential output
The QDR4 interface fixed frequency clock circuit is shown in the following figure.
UG1302 (v1.0) December 21, 2018
VCU128 Board User Guide
QDR4 Interface Clock
Figure 11:
Chapter 3: Board Component Descriptions
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