Xilinx VCU128 User Manual page 25

1.2V 168-ball BGA
○
Up to RL3-1866
○
The VCU128 XCVU37P FPGA RLDRAM3 interface performance is documented in the Virtex
UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923).
This memory system is connected to the XCVU37P HP banks 73, 74, and 75. The RLD3 0.6V
VTT termination voltage (net RLD3_VTERM_0V6) is sourced from TI TPS51200DR linear
regulator U92. The RLD3 memory interface bank VREF pins are not connected, which, coupled
with an XDC set_property INTERNAL_VREF constraint, invoke the INTERNAL VREF mode. The
connections between the RLD3 component memories and XCVU37P banks 73, 74, and 75 are
listed in the following table.
Table 7: RLD3 Memory 72-bit I/F to FPGA U1 Banks 73, 74, and 75
FPGA (U1) Schematic Net
Pin
K29
J30
K32
J31
L29
L31
L30
J32
K31
G30
H30
F31
G28
H29
G31
G32
H32
F28
E33
F29
E29
C32
F33
D30
D32
D29
UG1302 (v1.0) December 21, 2018
VCU128 Board User Guide
I/O Standard
Name
RLD3_72B_DQ0 SSTL12
RLD3_72B_DQ1 SSTL12
RLD3_72B_DQ2 SSTL12
RLD3_72B_DQ3 SSTL12
RLD3_72B_DQ4 SSTL12
RLD3_72B_DQ5 SSTL12
RLD3_72B_DQ6 SSTL12
RLD3_72B_DQ7 SSTL12
RLD3_72B_DQ8 SSTL12
RLD3_72B_DQ9 SSTL12
RLD3_72B_DQ10 SSTL12
RLD3_72B_DQ11 SSTL12
RLD3_72B_DQ12 SSTL12
RLD3_72B_DQ13 SSTL12
RLD3_72B_DQ14 SSTL12
RLD3_72B_DQ15 SSTL12
RLD3_72B_DQ16 SSTL12
RLD3_72B_DQ17 SSTL12
RLD3_72B_DQ18 SSTL12
RLD3_72B_DQ19 SSTL12
RLD3_72B_DQ20 SSTL12
RLD3_72B_DQ21 SSTL12
RLD3_72B_DQ22 SSTL12
RLD3_72B_DQ23 SSTL12
RLD3_72B_DQ24 SSTL12
RLD3_72B_DQ25 SSTL12
Chapter 3: Board Component Descriptions
Component Memory
Pin # Pin Name
D11 DQ0
E10 DQ1
C8 DQ2
C10 DQ3
C12 DQ4
B9 DQ5
B11 DQ6
A8 DQ7
A10 DQ8
J10 DQ9
K11 DQ10
K13 DQ11
L8 DQ12
L10 DQ13
L12 DQ14
M9 DQ15
M11 DQ16
N8 DQ17
D3 DQ18
E4 DQ19
C6 DQ20
C4 DQ21
C2 DQ22
B5 DQ23
B3 DQ24
A6 DQ25
Send Feedback
Ref. Des.
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
U39
www.xilinx.com
25