Fluke 4322 Operator's Manual page 116

4322
Operators Manual
The Status Byte Register can be read using the "*STB?" query, or by performing a serial
poll on the GPIB488 interface. If read with a serial poll, then Bit 6 is the RQS. If the
"∗STB?" query is used, then bit 6 is the MSS bit. All of the other bits are common to
both types of query.
Each of these status bits can cause a SRQ to occur when used with the GPIB488
interface. The Service Request Enable Register ("∗SRE" command ) determines which of
these flags are able to assert the SRQ line. This enable register has a matched set of bits
that each enables the designated bit to cause a SRQ, except for the RQS/MSS bit(s)
which cannot cause a SRQ. If you set this register to 20 ($14 hex), an SRQ will occur if
the MAV or the ERROR bit are set. The description of these bits are given as:
OPER: Operational Event Register Summary Bit (Bit 7)
This bit is set and clears by the Operational Summary bit whose status is derived from the
Operation Status Register (See the "STAT:OPER:" commands)
RQS: Requested Service (Bit 6)
Indicates that the SRQ line of the IEEE-488 interface has been asserted by the Controller.
This bit is cleared when a serial poll is performed on the Instrument, and is a part of the
status byte register when read with a serial poll. This bit only applies when used with the
GPIB488 interface.
MSS: Master Summary Status (Bit 6)
Indicates that an event or events occurred that caused the Controller to request service
from the Host, much like the RQS bit. Unlike the RQS bit, it is read-only and can be only
cleared when the event(s) that caused the service request are cleared.
ESB: Event Summary Bit (Bit 5)
Indicates if an enabled bit in the Standard Event Status Register became set.
MAV: Message Available Bit (Bit 4)
Indicates that at least one reply message is waiting in the response queue.
QUES: QUEStionable event register summary bit (Bit 3)
This bit is not supported.
ERR: Error Queue not empty (Bit 2)
Indicates that at least one command error message is waiting in the error message queue.
Use the "SYST:ERR?" query to get these messages.
RSB: Ready Summery Bit (Bit 0)
Indicates that an enabled bit in the Ready Status Register became set. Use the "*RSE"
command to enable the desired events.
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