Analog Devices ADE9000 Technical Reference Manual page 84

UG-1098
Addr. Name Bits
6
5
4
[3:2]
1
0
0x4B4 CRC_FORCE [15:1]
0
0x4B5 CRC_OPTEN 15
14
13
12
11
10
9
8
7
6
5
4
3
Bit Name Settings Description
PWR_SIGN_SEL[0]
RD_RST_EN
EGY_LD_ACCUM
RESERVED
EGY_TMR_MODE
EGY_PWR_EN
RESERVED
FORCE_CRC_UPDATE
CRC_WFB_TRG_CFG_EN
CRC_WFB_PG_IRQEN
CRC_WFB_CFG_EN
CRC_SEQ_CYC_EN
CRC_ZXLPSEL_EN
CRC_ZXTOUT_EN
CRC_APP_NL_LVL_EN
CRC_REACT_NL_LVL_EN
CRC_ACT_NL_LVL_EN
CRC_SWELL_CYC_EN
CRC_SWELL_LVL_EN
CRC_DIP_CYC_EN
CRC_DIP_LVL_EN
Rev. 0 | Page 84 of 86
ADE9000 Technical Reference Manual
Selects whether the REVAPx bit follows the sign
of the total or fundamental active power.
0 Total active power.
1 Fundamental active power.
Set this bit to enable the energy register read
with reset feature. If this bit is set, when one of
the xWATTHR, xVAHR, xVARH, xFWATTHR,
xFVAHR, and xFVARHR register is read, it is reset
and begins accumulating energy from zero.
If this bit is equal to zero, the internal energy
register is added to the user accessible energy
register. If the bit is set, the internal energy
register overwrites the user accessible energy
register when the EGYRDY event occurs.
Reserved.
This bit determines whether energy is
accumulated based on the number of 8 kSPS
samples or zero-crossing events configured in
the EGY_TIME register.
0 Accumulate energy based on 8 kSPS samples.
1 Accumulate energy based on the zero-crossing
selected by the ZX_SEL bits in the ZX_LP_SEL
register.
Set this bit to enable the energy and power
accumulator, when the run bit is also set.
Reserved.
Write this bit to force the configuration register
CRC calculation to start. When the calculation is
complete, the CRC_DONE bit is set in the
STATUS1 register.
Set this bit to include the WFB_TRG_CFG register
in the configuration register CRC calculation.
Set this bit to include the WFB_PG_IRQEN register
in the configuration register CRC calculation.
Set this bit to include the WFB_CFG register in
the configuration register CRC calculation.
Set this bit to include the SEQ_CYC register in
the configuration register CRC calculation.
Set this bit to include the ZX_LP_SEL register in
the configuration register CRC calculation.
Set this bit to include the CRC_ZXTOUT_EN register
in the configuration register CRC calculation.
Set this bit to include the APP_NL_LVL register in
the configuration register CRC calculation.
Set this bit to include the REACT_NL_LVL register in
the configuration register CRC calculation.
Set this bit to include the ACT_NL_LVL register in
the configuration register CRC calculation.
Set this bit to include the SWELL_CYC register in
the configuration register CRC calculation.
Set this bit to include the SWELL_LVL register in
the configuration register CRC calculation.
Set this bit to include the DIP_CYC register in the
configuration register CRC calculation.
Set this bit to include the DIP_LVL register in the
configuration register CRC calculation.
Reset Access
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R
0x0 R/W
0x0 R/W
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W