Analog Devices ADE9000 Technical Reference Manual page 83

ADE9000 Technical Reference Manual
Addr. Name Bits
0x4A2 WFB_TRG_CFG [15:11] RESERVED
10
9
8
7
6
5
4
3
2
1
0
0x4A3 WFB_TRG_STAT [15:12] WFB_LAST_PAGE
11
[10:0]
0x4AF CONFIG2 [15:13] RESERVED
12
[11:9]
[8:0]
0x4B0 EP_CFG [15:13] NOLOAD_TMR
[12:8]
7
Bit Name Settings Description
TRIG_FORCE
ZXCOMB
ZXVC
ZXVB
ZXVA
ZXIC
ZXIB
ZXIA
OI
SWELL
DIP
RESERVED
WFB_TRIG_ADDR
UPERIOD_SEL
HPF_CRN
RESERVED
RESERVED
PWR_SIGN_SEL[1]
Rev. 0 | Page 83 of 86
Reserved.
Set this bit to trigger an event to stop the
waveform buffer filling.
Zero-crossing on combined signal from VA, VB,
and VC.
Phase C voltage zero-crossing.
Phase B voltage zero-crossing.
Phase A voltage zero-crossing.
Phase C current zero-crossing.
Phase B current zero-crossing.
Phase A current zero-crossing.
Over current event in any phase.
Swell event in any phase.
Dip event in any phase.
These bits indicate which page of the waveform
buffer was filled last, when filling with fixed rate
data samples.
Reserved.
These bits hold the address of the last sample
put into the waveform buffer after a trigger
event occurred, which is within a sample or two
of when the actual trigger event occurred.
Reserved.
Set this bit to use a user configured line period,
in USER_PERIOD, for the VRMS½, 10 cycle rms/
12 cycle rms and resampling calculation. If this
bit is clear, the phase voltage line period selected
by the LP_SEL[1:0] bits in the ZX_LP_SEL register
is used.
High-pass filter corner (f
HPFDIS bit in the CONFIG0 register is equal to zero.
000 77.39 Hz.
001 39.275 Hz.
010 19.79 Hz.
011 9.935 Hz.
100 4.98 Hz.
101 2.495 Hz.
110 1.25 Hz.
111 0.625 Hz.
Reserved.
This register configures how many 8 kSPS
samples to evaluate the no load condition over.
000 64 samples.
001 128 samples.
010 256 samples.
011 512 samples.
100 1024 samples.
101 2048 samples.
110 4096 samples.
111 Disable no load threshold.
Reserved.
Selects whether the REVRPx bit follows the sign
of the total or fundamental reactive power.
0 Total reactive power.
1 Fundamental reactive power.
Reset
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
) enabled when the 0x6
3dB
0x0
0x0
0x0
0x0
UG-1098
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R
R/W
R
R/W