Analog Devices ADE9000 Technical Reference Manual page 73

ADE9000 Technical Reference Manual
Addr. Name Bits
0x406 MASK1 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Bit Name Settings Description
ERROR3
ERROR2
ERROR1
ERROR0
CRC_DONE
CRC_CHG
DIPC
DIPB
DIPA
SWELLC
SWELLB
SWELLA
RESERVED
SEQERR
OI
RESERVED
ZXIC
ZXIB
ZXIA
ZXCOMB
ZXVC
ZXVB
ZXVA
Rev. 0 | Page 73 of 86
Set this bit to enable an interrupt if ERROR3 occurs.
Issue a software reset or hardware reset to clear
this error.
Set this bit to enable an interrupt if ERROR2 occurs. 0x0
This interrupt is not maskable. Issue a software
reset or hardware reset to clear this error.
This interrupt is not maskable. Issue a software
reset or hardware reset to clear this error.
Set this bit to enable an interrupt when the
configuration register CRC calculation is complete,
after initiated by writing the FORCE_CRC_UPDATE
bit in the CRC_FORCE register.
Set this bit to enable an interrupt if any of the
registers monitored by the configuration register
CRC change value. The CRC_RSLT register holds
the new configuration register CRC value.
Set this bit to enable an interrupt when the
Phase C voltage enters a dip condition
Set this bit to enable an interrupt when the
Phase B voltage enters a dip condition.
Set this bit to enable an interrupt when the
Phase A voltage enters a dip condition.
Set this bit to enable an interrupt when the
Phase C voltage enters a swell condition.
Set this bit to enable an interrupt when the
Phase B voltage enters a swell condition.
Set this bit to enable an interrupt when the
Phase A voltage enters a swell condition.
Reserved.
Set this bit to enable an interrupt when on a
phase sequence error on the phase voltage
zero-crossings.
Set this bit to enable an interrupt when one of
the currents enabled in the OC_EN bits in the
CONFIG3 register enters an overcurrent condition.
Reserved.
Set this bit to enable an interrupt when a zero-
crossing is detected on the Phase C current
channel.
Set this bit to enable an interrupt when a zero-
crossing is detected on the Phase B current
channel.
Set this bit to enable an interrupt when a zero-
crossing is detected on the Phase A current
channel.
Set this bit to enable an interrupt when a zero-
crossing is detected on the combined signal
from VA, VB, and VC.
Set this bit to enable an interrupt when a zero-
crossing is detected on the Phase C voltage
channel.
Set this bit to enable an interrupt when a zero-
crossing is detected on the Phase B voltage
channel.
Set this bit to enable an interrupt when a zero-
crossing is detected on the Phase A voltage
channel.
UG-1098
Reset Access
0x0 R/W
R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R
0x0 R/W
0x0 R/W
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W