Analog Devices ADE9000 Technical Reference Manual page 61

ADE9000 Technical Reference Manual
Address Name
0x41D REACT_NL_LVL
0x41E APP_NL_LVL
0x41F PHNOLOAD
0x420 WTHR
0x421 VARTHR
0x422 VATHR
0x423 LAST_DATA_32
0x424 ADC_REDIRECT
0x425 CF_LCFG
0x472 PART_ID
0x474 TEMP_TRIM
0x480 RUN
0x481 CONFIG1
0x482 ANGL_VA_VB
0x483 ANGL_VB_VC
0x484 ANGL_VA_VC
0x485 ANGL_VA_IA
0x486 ANGL_VB_IB
0x487 ANGL_VC_IC
0x488 ANGL_IA_IB
0x489 ANGL_IB_IC
0x48A ANGL_IA_IC
0x48B DIP_CYC
0x48C SWELL_CYC
0x48F OISTATUS
0x490 CFMODE
0x491 COMPMODE
0x492 ACCMODE
0x493 CONFIG3
0x494 CF1DEN
0x495 CF2DEN
0x496 CF3DEN
0x497 CF4DEN
0x498 ZXTOUT
0x499 ZXTHRSH
0x49A ZX_LP_SEL
0x49C SEQ_CYC
0x49D PHSIGN
0x4A0 WFB_CFG
0x4A1 WFB_PG_IRQEN
0x4A2 WFB_TRG_CFG
0x4A3 WFB_TRG_STAT
Description
No load threshold in the total and fundamental reactive power datapath.
No load threshold in the total and fundamental apparent power datapath.
Phase no load register.
Sets the maximum output rate from the digital to frequency converter for the
total and fundamental active power for the CFx calibration pulse output. It is
recommended to write WTHR = 0x0010_0000.
Sets the maximum output rate from the digital to frequency converter for the
total and fundamental reactive power for the CFx calibration pulse output. It is
recommended to write VARTHR = 0x0010_0000.
Sets the maximum output rate from the digital to frequency converter for the
total and fundamental apparent power for the CFx calibration pulse output. It is
recommended to write VATHR = 0x0010_0000.
This register holds the data read or written during the last 32-bit transaction on
the SPI port.
This register allows any ADC output to be redirected to any digital datapath.
CFx calibration pulse width configuration register.
This register identifies the IC. If the ADE9000_ID bit = 1, the IC is the ADE9000.
Temperature sensor gain and offset, calculated during the manufacturing process.
Write this register to 1 to start the measurements.
Configuration Register 1.
Time between positive to negative zero-crossings on Phase A and Phase B voltages.
Time between positive to negative zero-crossings on Phase B and Phase C voltages.
Time between positive to negative zero-crossings on Phase A and Phase C voltages.
Time between positive to negative zero-crossings on Phase A voltage and current.
Time between positive to negative zero-crossings on Phase B voltage and current.
Time between positive to negative zero-crossings on Phase C voltage and current.
Time between positive to negative zero-crossings on Phase A and Phase B current.
Time between positive to negative zero-crossings on Phase B and Phase C current.
Time between positive to negative zero-crossings on Phase A and Phase C current.
Voltage RMS½ dip detection cycle configuration.
Voltage RMS½ swell detection cycle configuration.
Overcurrent status register.
CFx configuration register.
Computation mode register.
Accumulation mode register.
Configuration Register 3.
CF1 denominator register.
CF2 denominator register.
CF3 denominator register.
CF4 denominator register.
Zero-crossing timeout configuration register.
Voltage channel zero-crossing threshold register.
This register selects which zero-crossing and which line period measurement are
used for other calculations.
Number of line cycles used for phase sequence detection. It is recommended to
set this register to 1.
Power sign register.
Waveform buffer configuration register.
This register enables interrupts to occur after specific pages of the waveform
buffer are filled.
This register enables events to trigger a capture in the waveform buffer.
This register indicates the last page that was filled in the waveform buffer and
the location of trigger events.
Rev. 0 | Page 61 of 86
UG-1098
Reset Access
0x0000FFFF R/W
0x0000FFFF R/W
0x00000000 R
0x0000FFFF R/W
0x0000FFFF R/W
0x0000FFFF R/W
0x00000000 R
0x001FFFFF R/W
0x00000000 R/W
0x00100000 R
0x00000000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R
0x0000 R
0x0000 R
0x0000 R
0x0000 R
0x0000 R
0x0000 R
0x0000 R
0x0000 R
0xFFFF R/W
0xFFFF R/W
0x0000 R
0x0000 R/W
0x0000 R/W
0x0000 R/W
0xF000 R/W
0xFFFF R/W
0xFFFF R/W
0xFFFF R/W
0xFFFF R/W
0xFFFF R/W
0x0009 R/W
0x001E R/W
0x00FF R/W
0x0000 R
0x0000 R/W
0x0000 R/W
0x0000 R/W
0x0000 R/W