Full-Scale Codes; Power And Filter-Based Rms Measurement Algorithms - Analog Devices ADE9000 Technical Reference Manual

ADE9000 Technical Reference Manual
Voltage Channel Measurements
Table 7 indicates the registers that hold voltage channel
measurements and the rate at which they update.
Table 7. Voltage Channel Measurement Update Rates
Register Name Description
AV_SINC_DAT VA sinc4 filter output
BV_SINC_DAT VB sinc4 filter output
CV_SINC_DAT VC sinc4 filter output
AV_LPF__DAT VA sinc4 + IIR LPF filter output
BV_LPF__DAT VB sinc4 + IIR LPF filter output
CV_LPF__DAT VC sinc4 + IIR LPF filter output
AV_PCF Instantaneous current on VA
BV_PCF Instantaneous current on VB
CV_PCF Instantaneous current on VC
AVRMS Filtered-based total rms of VA
BVRMS Filtered-based total rms of VB
CVRMS Filtered-based total rms of VC
VPEAK Peak current channel sample; see
the Peak Detection section
APERIOD Line period measurement on VA
BPERIOD Line period measurement on VB
CPERIOD Line period measurement on VB
COM_PERIOD Line period measurement on
combined signal from VA, VB, VC;
see the Combined Voltage Zero-
Crossing section
ANGLx_xxx Voltage to current or current to
current phase angle; see the
Angle Measurement section
Voltage Channel Gain
The xVGAIN registers can be used to calibrate the voltage
channel of each phase. The xVGAIN register has the same
scaling as the xIGAIN register. See the Current Channel Gain,
xIGAIN section for the equation.

FULL-SCALE CODES

Table 8 gives the expected codes when the ADC inputs are at
full scale with PGA gain set to 1.
Table 8. Full-Scale ADC Codes
Parameter
Sinc4 Output at 32 ksps
Dec Output at 8 ksps
xPCF at 8 ksps
Total IRMS and VRMS
Fundamental IRMS and VRMS
Total WATT, VAR, and VA
Fundamental WATT, VAR, and VA
Fast RMS½
10 Cycle RMS/12 Cycle RMS
Resampled Data
Update Rate
32 ksps
32 ksps
32 ksps
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
f = 8 ksps
DSP
CLKIN/24 =
1024 ksps
Output Code
67,107,786
74,518,668
74,532,013
52,702,092
52,702,092
20,694,066
20,694,066
52,702,092
52,702,092
18,196
Rev. 0 | Page 13 of 86
POWER AND FILTER-BASED RMS MEASUREMENT
ALGORITHMS
Filter-Based Total RMS
The ADE9000 offers current and voltage rms measurements
that are calculated by squaring the input signal, low-pass
filtering, and then taking the square root of the result.
The low-pass filter, LPF2, extracts the rms value, attenuating
harmonics of a 50 Hz or 60 Hz fundamental by at least 64 dB so
that, at full scale, the variation in the calculated rms value is
very small, ±0.064% error. Note that the rms reading variation
increases as the input signal gets smaller because the noise in
the measurement increases.
Note that the xRMS register does not read 0 with the xP and xN
inputs shorted together.
The filter based rms has a bandwidth of 3.2 kHz
The rms calculations, one for each channel, AIRMS, BIRMS,
CIRMS, NIRMS, AVRMS, BVRMS, and CVRMS, are updated
every 8 ksps. The ISUMRMS calculation uses the same method
to calculate ISUMRMS, where ISUM = IA + IB + IC ± IN, and
also updates at 8 ksps (see the Neutral Current RMS, Vector
Current Sum section for more information).
The xRMS value at full scale is 52,702,092 (decimal). The full
scale is a function of PGA gain.
full scale input
=
full scale
PGA
For high performance at small input signals, below 1000:1, it is
recommended to calibrate the offset of this measurement using
the xRMSOS register. It is recommended to calibrate the offset
at the smallest input signal that requires good performance; do
not calibrate this measurement with zero input signal.
The following equation indicates how the xRMSOS register
value modifies the result in the xRMS register.
= +
xxRMS xxRMS 2
0
where xxRMS
is the initial xRMS register value before offset
0
calibration.
For example, if the expected the AIRMS at 1000:1 is
52,702,092/1000 = 52,702 (decimal) and the AIRMS register
reading is 53280 (decimal), the offset calibration register is
2
−
52702 53280
=
AIRMSOS
15
2
Table 9 shows the rms settling time to 99% of full scale for a
50 Hz signal.
Table 9. RMS Settling Time
Configuration
Integrator On, HPF On, and LPF2 On
Integrator Off, HPF On, and LPF2 On
UG-1098
at PGA GAIN1
GAIN
15 ×
2 xxRMSOS
2
= − =
1869 d 0 xFFFF8B
RMS Settling Time,
FS = 99% (sec)
0.54
0.48
8