Register Details - Analog Devices ADE9000 Technical Reference Manual

ADE9000 Technical Reference Manual
Address Name
0x6B8 CVRMS1012_2
0x6B9 NI_PCF_2
0x6BA NIRMS_2
0x6BB NIRMSONE_2
0x6BC NIRMS1012_2

REGISTER DETAILS

Table 31 details the registers of the
Table 31. Register Details
Addr. Name Bits
0x060 CONFIG0 [31:14] RESERVED
13
12
11
10
9
8
7
6
5
4
3
2
Description
SPI burst read accessible. Registers organized by phase. See CVRMS1012.
SPI burst read accessible. Registers organized by phase. See NI_PCF.
SPI burst read accessible. Registers organized by phase. See NIRMS.
SPI burst read accessible. Registers organized by phase. See NIRMSONE.
SPI burst read accessible. Registers organized by phase. See NIRMS1012.
ADE9000 that have bit fields. Additional registers listed in Table 30 do not have bit fields.
Bit Name Settings Description
DISRPLPF
DISAPLPF
ININTEN
VNOMC_EN
VNOMB_EN
VNOMA_EN
RMS_SRC_SEL
ZX_SRC_SEL
INTEN
MTEN
HPFDIS
RESERVED
Reserved.
Set this bit to disable the low-pass filter in the
total reactive power datapath.
Set this bit to disable the low-pass filter in the
total active power datapath.
Set this bit to enable the digital integrator in the
neutral current channel.
Set this bit to use the nominal phase voltage
rms, V , in the computation of Phase C total
NOM
apparent power, CVA.
Set this bit to use the nominal phase voltage
rms, V , in the computation of Phase B total
NOM
apparent power, BVA.
Set this bit to use the nominal phase voltage
rms, V , in the computation of Phase A total
NOM
apparent power, AVA.
This bit selects which samples are used for the
RMS½ and 10 cycle rms/12 cycle rms calculation.
0 xI_PCF waveforms, after the high-pass filter and
integrator.
1 ADC samples, before the high-pass filter and
integrator.
This bit selects whether data going into the zero-
crossing detection circuit comes before the
high-pass filter, integrator, and phase
compensation or afterwards.
0 After the high-pass filter, integrator, and phase
compensation.
1 Before the high-pass filter, integrator, and phase
compensation.
Set this bit to enable the integrators in the phase
current channels. The neutral current channel
integrator is managed by the ININTEN bit in the
CONFIG0 register.
Set this bit to enable multipoint phase and gain
compensation. If enabled, an additional gain
factor, xIGAIN0 through xIGAIN5, is applied to
the current channel based on the xIRMS current
rms amplitude and the MTTHR_Lx and
MTTHR_Hx register values.
Set this bit to disable high-pass filters in all the
voltage and current channels.
Reserved.
Rev. 0 | Page 65 of 86
UG-1098
Reset Access
0x00000000 R/W
0x00000000 R/W
0x00000000 R/W
0x00000000 R/W
0x00000000 R/W
Reset Access
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R