Analog Devices ADXL180 iMEMS Manual

Configurable, high g, accelerometer

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FEATURES

Wide sensor range: 50 g to 500 g

Adjustable filter bandwidth: 100 Hz to 800 Hz

Configurable communication protocol

2-wire, current mode bus interface

Selectable sensor data resolution: 8 bit or 10 bit

Continuous auto-zero

Fully differential sensor and interface circuitry

High resistance to EMI/RFI

Sensor self-test

5.0 V to 14.5 V operation

8 bits of user-defined OTP memory

32-bit electronic serial number

Dual device per bus option

APPLICATIONS

Crash sensing

V/Q

SCI

MOD

REF

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

FUNCTIONAL BLOCK DIAGRAM

ADXL180

OSCILLATOR/

OTP

TIMING

FUSE

GENERATOR

ROM

3-POLE

DIFF

DEMOD

BESSEL

SENSOR

AMP

FILTER

SCO

iMEMS Accelerometer

GENERAL DESCRIPTION

The ADXL180 iMEMS® accelerometer is a configurable, single

axis, integrated satellite sensor that enables low cost solutions

for front and side impact airbag applications. Acceleration data

is sent to the control module via a digital 2-wire current loop

interface bus. The communication protocol is programmable for

compatibility with various automotive interface bus standards.

The sensor g range is configurable to provide full-scale ranges

from ±50 g to ±500 g. The sensor signal third-order, low-pass

Bessel filter bandwidth is configurable at 100 Hz, 200 Hz,

400 Hz, and 800 Hz.

The 10-bit analog-to-digital converter (ADC) allows either 8-bit

or 10-bit acceleration data to be transmitted to the control module.

Each part has a unique electronic serial number. The device is

rated for operation from −40°C to +125°C and is available in a

5 mm × 5 mm LFCSP package.

SERIAL

NUMBER

TRIMS

CONFIGURATION

DATA

10-

AUTO-

BIT

STATE

ZERO

ADC

MACHINE

SELF-

TEST

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

Configurable, High g,

ADXL180

COMM

PORT

INTERFACE

SYNC

DETECT

PROGRAM

INTERFACE

VOLTAGE

REGULATOR

SUPPLY

MONITOR

www.analog.com

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Summary of Contents for Analog Devices ADXL180 iMEMS

Page 1: Features
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Page 2: Table Of Contents
ADXL180 TABLE OF CONTENTS Features ....................1 Phase 3: Self-Test Diagnostic ............ 35 Applications ..................1 Phase 4: Auto-Zero Initialization ..........38 General Description ................. 1 Phase 5: Normal Operation ............38 Functional Block Diagram .............. 1 Signal Range and Filtering ............39 Revision History ................
Page 3: Revision History
ADXL180 RG[2:0] ..................51 SVD ....................53 MD[1:0] ..................52 CUPAR and CUPRG ..............53 SYEN ..................... 53 Axis of Sensitivity ................54 AZE ....................53 Branding ................... 55 ERC ....................53 Outline Dimensions ................ 56 DAT ....................53 Ordering Guide ................56 REVISION HISTORY 8/08—Revision 0: Initial Version Rev.
Page 4: Specifications
ADXL180 SPECIFICATIONS = −40°C to +125°C, V − V = 5.0 V to 14.5 V, f = 400 Hz, acceleration = 0 g, unless otherwise noted. Table 1. Parameter Symbol Unit Test Conditions/Comments SENSOR Scale Factor Measurement frequency: 100 Hz 50 g Range See Table 37 8-Bit Data...
Page 5 ADXL180 Parameter Symbol Unit Test Conditions/Comments REGULATOR VOLTAGE MONITOR Regulator Operating Voltage 4.20 Power-Up Reset Voltage 3.77 4.23 See Figure 31 Overvoltage Level 4.95 See Figure 31 Reset Hysteresis Voltage 0.12 HYST COMMUNICATIONS INTERFACE Quiescent (Idle) Current LDLE Modulation Current Signal Current 37.7 IDLE...
Page 6 ADXL180 Parameter Symbol Unit Test Conditions/Comments ASYNCHRONOUS MODE TIMING Message Transmission Period Phase 2, Mode 0 μs ADIFX compatible All Other Phases and Modes μs Initialization State (Phase 1) Device Data State (Phase 2) Mode 0 4.10 Mode 1 Mode 2 Mode 3 Self-Test State (Phase 3) Self-Test Time...
Page 7: Absolute Maximum Ratings
ADXL180 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2. may cause permanent damage to the device. This is a stress Parameter Rating rating only; functional operation of the device at these or any Supply Voltage (V −...
Page 8: Pin Configuration And Function Descriptions
Mnemonic Description Reserved for Analog Devices Use Only. V or do not connect. Reserved for Analog Devices, Inc., Use Only. Do not connect. Negative Bus Voltage. Reserved for Analog Devices Use Only. V or do not connect. Voltage Regulator Bypass Capacitor.
Page 9: Terminology
ADXL180 TERMINOLOGY Idle Current Full-Scale Range (FSR) Idle current is the current of the device when at rest, waiting for The full-scale range of a device, also referred to as the dynamic a synchronization pulse, or in between current modulation. range, is the maximum and minimum g level that reports on the Modulation Current output following the internal filtering.
Page 10: Theory Of Operation
ADXL180 THEORY OF OPERATION OVERVIEW sensor is such that the displacement signal is differential between the two measurement channels. Using the fully The ADXL180 is a complete satellite system, including differential sensor and an antiphase clocking scheme helps acceleration sensor, data filtering, digital protocol functionality, reject electrical environmental noise (see Figure 5).
Page 11: Signal Processing
ADXL180 SIGNAL PROCESSING SYNCHRONOUS OPERATION AND DUAL DEVICE The ADXL180 contains an on-board set of signal processing blocks both prior to and after ADC conversion. The first stage is In a point-to-point bus topology, the ADXL180 supports asyn- a fully differential, switched capacitor, low-pass, three-pole chronous transmission of data to the receive device every 228 μs, Bessel filter.
Page 12 ADXL180 User-Programmed Configuration Application Layer (ISO Layer 7) At each of these previously described points in the system, the The serial number and configuration data transmission mode ADXL180 is highly configurable for different applications. The and self-test (internal self-test pass/fail discrimination or organization and configurable items are briefly described in this external self-test data evaluation).
Page 13: Physical Interface
ADXL180 PHYSICAL INTERFACE CURRENT MODULATION APPLICATION CIRCUIT When the ADXL180 device is powered on, it uses current A typical application circuit is shown in Figure 6. The two capa- modulation to transmit data. Normally, the device pulls I citors shown in Figure 6 are typically ceramic, X7R, multilayer IDLE current.
Page 14: Manchester Data Encoding
ADXL180 MANCHESTER DATA ENCODING Table 6. MAN Options Manchester Start To encode data within the current modulation, the ADXL180 Coding Bits Logic 0 Logic 1 uses Manchester encoding. Manchester encoding works on the Manchester-1 1, 0 Falling edge Rising edge principle of transitions representing binary 1s and 0s, as shown (Default) in Figure 8.
Page 15: Communications Timing And Bus Topologies
ADXL180 COMMUNICATIONS TIMING AND BUS TOPOLOGIES ASYNCHRONOUS COMMUNICATION ADC SAMPLE LOOP CURRENT DATA FRAME DATA FRAME IDLE TIME DURING PHASE 2, MODE 0 TIMES THE NUMBER OF BITS TRANSMITTED Figure 10. Asynchronous Mode Data Transmission Timing The ADXL180 data transmissions in their default mode run Configuring the ADXL180 for Synchronous Operation asynchronous to the control module.
Page 16 , consult Analog Devices, Inc., applications support for a synchronization pulse is detected. If the BDE bit is set, the further information on application specific pulse recognition.
Page 17: Synchronous Communication Mode-Dual Device
ADXL180 Synchronous Single Device Point-to-Point Topology ADXL180 devices to share a single pair of wires from the control module for power and communications. This is A single device is wired in the point-to-point configuration as accomplished using time division multiplexing where each shown in Figure 13.
Page 18 ADXL180 VOLTAGE SYNC DETECT/ BLANKING DEVICE 1 DISCHARGE CURRENT ADXL180 RETURN CURRENT DEVICE 1 DEVICE 1 DATA FRAME ADC BUSY DEVICE 1 SYNC DETECT/ BLANKING DEVICE 2 ADXL180 RETURN CURRENT DEVICE 2 DEVICE 2 DATA FRAME ADC BUSY DEVICE 2 TIME SLOT A TIME SLOT B DEVICE 1...
Page 19 ADXL180 Configuring Synchronous Operation The autodelay mode allows two identically configured devices to be wired in a series configuration. The two devices automatically Delay Selection configure the two node network upon power up. The configura- As shown in Table 9, the user can select the data timing of the tion bit (ADME) must be set to enable the autodelay mode.
Page 20 ADXL180 Dual Device Synchronous Series Topology CENTER MODULE The two devices are wired in a series configuration as shown in Figure 16. The series configuration can be configured to run in either of two modes: fixed delay or autodelay. These modes are DEVICE 1 DEVICE 2 configured using the FDLY and ADME bits in the configuration...
Page 21: Data Frame Definition
ADXL180 DATA FRAME DEFINITION DATA FRAME TRANSMISSION FORMAT DATA BITS START START BIT 0 BIT 1 LOOP CURRENT IDLE DATA BITS START START BIT 0 BIT 1 LOGIC SIGNAL AT CONTROL MODULE DECODER ‘0’ ‘1’ TIME Figure 17. Data Message Timing (Manchester-1, Bit Coding) •...
Page 22 ADXL180 CREG BIT NAME TRANSMITTED FIRST START STATE 10-BIT DATA BITS VECTOR START STATE 8-BIT DATA BITS VECTOR START 10-BIT DATA BITS START 8-BIT DATA BITS START STATE 10-BIT DATA BITS VECTOR START STATE 8-BIT DATA BITS VECTOR START 10-BIT DATA BITS START 8-BIT DATA...
Page 23: Acceleration Data Coding
ADXL180 ACCELERATION DATA CODING Table 14. 8-Bit Full Sensor Data Range Coding Binary (Twos 01 1111 1111 Decimal Complement) Description +127 0x7F 0111 1111 Most positive (+FS) 01 1111 1110 acceleration value 01 1111 1101 +126 0x7E 0111 1110 … +125 0x7D 0111 1101...
Page 24: State Vector Coding
ADXL180 STATE VECTOR CODING The 3-bit state vector field contains a code that defines the meaning of the data contained in the 8- or 10-bit data field. Table 18. SVD Data Bit Options These definitions are listed in Table 19. When selected, the 3-bit Definition state vector is appended to the 8- or 10-bit data field and State vector is enabled (default).
Page 25: Transmission Error Detection Options
ADXL180 TRANSMISSION ERROR DETECTION OPTIONS calculation is performed from MSB to LSB on the entire data frame. The CRC state registers are initialized to zero. Therefore, There are two error checking methods available: a 3-bit CRC when checking the result of the transmission, the final CRC and a 1-bit parity check.
Page 26: Application Layer: Communication Protocol State Machine
ADXL180 APPLICATION LAYER: COMMUNICATION PROTOCOL STATE MACHINE Table 21. ADXL180 Start-Up Sequence Summary Phase 1 Phase 4 Auto-Zero Phase 5 Name Initialization Phase 2 Device Data Phase 3 Self-Test Initialization Run Time Function Power-on reset None Sequence self-test Fast auto-zero Slow auto- pattern zero...
Page 27 ADXL180 Influence of MD On Data Range Table 23. MD Settings and Device Data Ranges Mode (Device Data) Data Range 0: ADIFX Full (All Configuration Data, Serial Number, and Reduced Manufacturer ID) Configuration error Configuration error 1: Range Data Only Full (Limited Range Selection) Reduced...
Page 28: Phase 2: Mode Description
ADXL180 PHASE 2: MODE DESCRIPTION Asynchronous Mode Mode 0 The device data is transmitted at a time interval of 456 μs based on the internal clock of the ADXL180. The 456 μs period is The Mode 0 option for Phase 2 transmits the entire contents of twice the normal transmission time interval of 228 μs.
Page 29 Table 29. In this case, the error state is MFGID2|MFGID2|MGFID0 101b Analog Devices entered immediately instead of entering Phase 1. See Table 39 identification code for the error coding. When both Phase 2 Mode 1 and the 10-bit...
Page 30 ADXL180 Mode 2 used (see the Data Frame Transmission Format section). Therefore, the positive and negative full-scale ends of the sensor Device Data data range overlap with the device data and status/error codes. When Mode 2 is selected, the device data that is transmitted The state vector distinguishes between the types of transmitted consists of the UREG byte, four configuration register bytes (see data.
Page 31 ADXL180 PHASE 1 PHASE 2 PHASE 3 ST DATA/ STATUS SERIAL NUMBER 9 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 31 32 USER BITS DELIMITER 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Figure 24.
Page 32 ADXL180 8-Bit Data 10-Bit Data Decimal Decimal Data Type Description −126 0x82 −504 0x208 Undefined Unused −127 0x81 −508 0x204 Undefined Unused ±100 g measurement range −128 0x80 −512 0x200 Status code Table 31. Phase 2 Mode 2 Delimiter Coding 8-Bit Data 10-Bit Data Range...
Page 33 Table 33. Phase 2 Mode 3 Device Data Mapping Device Data Nybble No. Definition Binary Code Nybble Sent Protocol ID 0011 Number of nybbles sent 10000 0000 Manufacturer Analog Devices 1010 Sensor type Accelerometer 00001 0001 Sensor range 100 g 0000 0000 50 g...
Page 34 ADXL180 Device Data Nybble No. Definition Binary Code Nybble Sent Serial number (Bits[23:20]) XXXX XXXX Serial number (Bits[19:16]) XXXX XXXX Serial number (Bits[15:12]) XXXX XXXX Serial number (Bits[11:8]) XXXX XXXX Serial number (Bits[7:4]) XXXX XXXX Serial number (Bits[3:0]) XXXX XXXX Data Nybble 1 is transmitted first.
Page 35: Phase 3: Self-Test Diagnostic
ADXL180 Decimal Data Type Description −497 0x20F Nybble Number Device Data Nybble 16 −498 0x20E Nybble Number Device Data Nybble 15 −499 0x20D Nybble Number Device Data Nybble 14 −500 0x20C Nybble Number Device Data Nybble 13 −501 0x20B Nybble Number Device Data Nybble 12 −502 0x20A...
Page 36 ADXL180 PHASE 3 PHASE 4 LOOP CURRENT IDLE TIME Figure 26. External Self-Test Control Timing Calculate difference (V ) − (V ) and compare to Internal Self-Test STZ1 specified minimum and maximum difference. The internal mode self-test applies an electrostatic force to Calculate the absolute difference (V ) −...
Page 37 ADXL180 ENTER SELF-TEST CYCLE CALCULATE STD = V – V WAIT 32 SAMPLES STZ1 AVERAGE 64 SAMPLES < STD < STD STZ1 ASSERT SELF-TEST SIGNAL CALCULATE STZ = |V – V STZ1 STZ2 WAIT 32 SAMPLES STZ ≤ 4 LSB* AVERAGE 64 SAMPLES *10-BIT LSB INCREMENT PASS COUNT...
Page 38: Phase 4: Auto-Zero Initialization
ADXL180 specifics. No acceleration data is transmitted when the PHASE 4: AUTO-ZERO INITIALIZATION ADXL180 is in the error state. If auto-zero is not enabled, upon entering Phase 4, the PHASE 5: NORMAL OPERATION ADXL180 immediately passes from Phase 4 to Phase 5. If auto-zero is not enabled, upon entering Phase 5, the Fast Auto-Zero Mode ADXL180 transmits the measured (raw) acceleration signal...
Page 39: Signal Range And Filtering
ADXL180 SIGNAL RANGE AND FILTERING THREE-POLE BESSEL FILTER TRANSFER FUNCTION OVERVIEW The three-pole, low-pass Bessel filter has a selectable −3 dB Table 38. FC Low-Pass Filter Bandwidth Frequency Select corner (f ). The corner can be set to 100 Hz, 200 Hz, 400 Hz, or Codes 800 Hz by programming the filter corner (FC) bits in the −3 dB LP Frequency...
Page 40 ADXL180 Offset Drift Monitoring appropriate error code is sent in the next data frame transmitted to the control module (see the Offset Error/Offset Drift Cumulative offset drift is monitored during the normal Monitoring section). This message is sent continuously until operation of the ADXL180.
Page 41: Error Detection
ADXL180 ERROR DETECTION PARITY ERROR DUE TO COMMUNICATIONS OVERVIEW PROTOCOL CONFIGURATION BIT ERROR The ADXL180 monitors its internal operation and reports As shown in Table 39, an error code is generated if the parity of errors. The error reporting codes differ depending on whether the ADXL180 device OTP memory is incorrect.
Page 42: Self-Test Error
ADXL180 SELF-TEST ERROR the ADXL180 continuously monitors long term offset drift. If the long-term offset correction exceeds the maximum specified In the ADXL180, self-test is automatically run during Phase 3. value, then an offset error is reported. This error is reported If the internal self-test mode is selected, then the device enters independent of whether or not the auto-zero functionality has into the self-test routine as detailed in Figure 27 and Figure 28.
Page 43: Test And Diagnostic Tools
ADXL180 TEST AND DIAGNOSTIC TOOLS SIGNAL CHAIN INPUT TEST PIN ANALOG SIGNAL CHAIN OUTPUT TEST PIN The V signal chain input test pin allows the excitation of the The V analog signal chain output test pin provides access to signal chain from the input of the sensor interface circuitry the sensor signal chain analog output voltage at the output of (sensor amplifier) through to the output of the current mode the Bessel filter.
Page 44: Configuration Specification
ADXL180 CONFIGURATION SPECIFICATION the ADXL180 via voltage modulation of the V pin with OVERVIEW respect to the V pin. This signal uses pulse duration modula- The ADXL180 configuration mode allows access to the user- tion to combine the clock and digital data. The clock and data programmable nonvolatile configuration registers used to are encoded as shown in Figure 33.
Page 45: Configuration Mode Transmit Communications Protocol
ADXL180 DATA FRAME (18 BITS) TRANSMITTED START STATE FIRST DATA ADDRESS BITS VECTOR Figure 36. Configuration Mode Transmit Data Frame CONFIGURATION MODE TRANSMIT This is an 18-bit protocol (including the two start bits). Although similar to the ADIFX protocol, it is different in that parity, and COMMUNICATIONS PROTOCOL not CRC, is used as the error checking code.
Page 46: Configuration Mode Command (Receive) Communications Protocol
ADXL180 CONFIGURATION MODE COMMAND (RECEIVE) operation and a 1 indicates a read operation. The parity bit is set for even parity. The parity bit should be set to 0 or 1 to make the COMMUNICATIONS PROTOCOL total number of 1s in the data frame even. The data is The 8-bit configuration register data is passed to the ADXL180 transmitted LSB first as shown in Table 42.
Page 47: Configuration Mode Communications Handshaking
ADXL180 CONFIGURATION MODE COMMUNICATIONS written to RAM, read back from the RAM, and transmitted to the user’s test/configuration system as a handshake. This provides HANDSHAKING a data integrity check for data write commands. If there is an Configuration mode communications uses a handshaking attempt to write data to a RAM register after the CUPRG bit is protocol.
Page 48: Configuration And User Data Registers
ADXL180 CONFIGURATION AND USER DATA REGISTERS The ADXL180 can be configured to send this data as part of the device data transmitted during Phase 2 of the power-up The configuration and user data registers are the user register, initialization sequence. UREG, and the three configuration registers, CREG0, CREG1, PROGRAMMING THE CONFIGURATION AND USER and CREG2 (see Table 44).
Page 49: Otp Programming Conditions And Considerations
ADXL180 FROM RECEIVE SERIAL PORT TO TRANSMIT SERIAL PORT AND CONFIGURATION CONTROL LOGIC PROGRAM DATA FUSE CUPRG Figure 40. Configuration Mode RAM and OTP Register Structure handshake back to the command module. Do not attempt to The CUPRG bit is automatically programmed to the locked state (1) at the end of the configuration/user data OTP fuse write to the configuration registers or attempt another OTP programming sequence.
Page 50: Configuration Register Reference
ADXL180 CONFIGURATION REGISTER REFERENCE The following tables define the codes for each programmable field in the three configuration registers (CREG0, CREG1, and CREG2). The default setting (unprogrammed state) of all bits in all configuration registers is zero. As a result, the default configuration of the ADXL180 is compatible with the ADIFX operation mode and communication protocol as implemented in the ADXS101 satellite transmitter.
Page 51: Ud[7:0] User Data Bits
ADXL180 UD[7:0] USER DATA BITS FDLY The user register is for arbitrary user data. It does not have any Table 49. Fixed Delay Mode influence on sensor operation. This data is transmitted during FDLY Definition Phase 2 of the state machine. For more information on trans- Fixed delay mode disabled (default).
Page 52: Md[1:0]
ADXL180 MD[1:0] Table 56. Phase 2 (Device Data) Transmission Mode Select Table 55. Phase 2 (Device Data) Transmission Mode Select Codes Codes Data Name Definition Device OK Mode 0 ADIFX mode device data Range Mode 1 Range data only (range selection limited) Delimiter Mode 2...
Page 53: Syen
ADXL180 SYEN Table 58. Sync Enable (SYEN) Options Table 61. DAT Data Bit Options SYEN Definition Definition Synchronization pulse disabled. Device transmits data 10-bit data sensor data transmitted. 8-bit Phase 2 according to state machine based on internal clock configuration data left-justified in 10-bit data frame every 228 μs when powered (default).
Page 54: Axis Of Sensitivity
ADXL180 AXIS OF SENSITIVITY = 0g ADXL180 XXXX XXXX = –1g = +1g = 0g = 0g EARTH’S SURFACE Figure 41. Output Response vs. Orientation Rev. 0 | Page 54 of 56...
Page 55: Branding
ADXL180 BRANDING 180Z CL CL CL CL CL Figure 42. ADXL180 Laser Brand Table 64. ADXL180 Branding Key Line Text Description Accelerometer 180Z ADXL180Z Year code Week code Lot code Country of origin (Philippines) Rev. 0 | Page 55 of 56...
Page 56: Outline Dimensions
Package Option ADXL180WCPZ-RL −40°C to +125°C 16-Lead LFCSP_LQ CP-16-8 Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07544-0-8/08(0) Rev. 0 | Page 56 of 56...

Analog Devices ADXL180 iMEMS Manual

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FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

Need help?

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Summary of Contents for Analog Devices ADXL180 iMEMS

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