Analog Devices ADE9000 Technical Reference Manual page 82

High performance, multiphase energy and power quality monitoring ic
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UG-1098
Addr. Name
Bits
0x4A0 WFB_CFG
[15:13] RESERVED
12
[11:10] RESERVED
[9:8]
[7:6]
5
4
[3:0]
Bit Name
Settings Description
WF_IN_EN
WF_SRC
WF_MODE
WF_CAP_SEL
WF_CAP_EN
BURST_CHAN
Rev. 0 | Page 82 of 86
ADE9000 Technical Reference Manual
Reserved.
This setting determines whether the IN waveform
samples are read out of the waveform buffer
through the SPI.
0 IN waveform samples are not read out of
waveform buffer through the SPI.
1 IN waveform samples are read out of waveform
buffer through the SPI.
Reserved.
Waveform buffer source and DREADY (data
ready update rate) selection.
00 Sinc4 output at 32 kSPS.
01 Reserved.
10 Sinc4 + IIR LPF output at 8 kSPS.
11 Current and voltage channel waveform samples,
processed by the DSP (xI_PCF, xV_PCF) at 8 kSPS.
Fixed data rate waveforms filling and trigger
based modes.
00 Stop when waveform buffer is full.
01 Continuous fill—stop only on enabled trigger
events.
10 Continuous filling—center capture around
enabled trigger events.
11 Continuous fill—save event address of enabled
trigger events.
This bit selects whether the waveform buffer is
filled with resampled data or fixed data rate
data, selected in the WF_CAP_SEL bits.
0 Resampled data.
1 Fixed data rate data.
When this bit is set, a waveform capture is started.
0 The waveform capture is disabled. The waveform
buffer contents are maintained.
1 The waveform capture is started, according to
the type of capture in WF_CAP_SEL and the
WF_SRC bits when this bit goes from a 0 to a 1.
Selects which data to read out of the waveform
buffer through SPI.
0000 All channels.
0001 IA and VA.
0010 IB and VB.
0011 IC and VC.
1000 IA.
1001 VA.
1010 IB.
1011 VB.
1100 IC.
1101 VC.
1110 IN if WF_IN_EN = 1 in the WFB_CFG register.
1111 Single address read (SPI burst read mode is
disabled).
Reset
Access
0x0
R
0x0
R/W
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W

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