Analog Devices ADE9000 Technical Reference Manual page 71

ADE9000 Technical Reference Manual
Addr. Name Bits
8
7
6
5
4
3
2
1
0
0x405 MASK0 [31:26] RESERVED
25
24
23
22
21
20
19
18
Bit Name Settings Description
REVPSUM3
REVPSUM2
REVPSUM1
SWELLC
SWELLB
SWELLA
DIPC
DIPB
DIPA
TEMP_RDY_MASK
MISMTCH
COH_WFB_FULL
WFB_TRIG
THD_PF_RDY
RMS1012RDY
RMSONERDY
PWRRDY
Rev. 0 | Page 71 of 86
This bit indicates the sign of the last CF3 pulse. A
zero indicates that the pulse was from negative
energy and a one indicates that the energy was
positive. This bit is updated when a CF3 pulse is
output, when the CF3 pin goes from high to low.
This bit indicates the sign of the last CF2 pulse. A
zero indicates that the pulse was from negative
energy and a one indicates that the energy was
positive. This bit is updated when a CF2 pulse is
output, when the CF2 pin goes from high to low.
This bit indicates the sign of the last CF1 pulse. A
zero indicates that the pulse was from negative
energy and a one indicates that the energy was
positive. This bit is updated when a CF1 pulse is
output, when the CF1 pin goes from high to low.
This bit is equal to one when the Phase C
voltage is in the swell condition and is zero
when it is not in a swell condition.
This bit is equal to one when the Phase B voltage
is in the swell condition and is zero when it is not
in a swell condition.
This bit is equal to one when the Phase A
voltage is in the swell condition and is zero
when it is not in a swell condition.
This bit is equal to one when the Phase C
voltage is in the dip condition and is zero when
it is not in a dip condition.
This bit is equal to one when the Phase B voltage
is in the dip condition and is zero when it is not
in a dip condition
This bit is equal to one when the Phase A
voltage is in the dip condition and is zero when
it is not in a dip condition.
Reserved.
Set this bit to enable an interrupt when a new
temperature measurement is available.
Set this bit to enable an interrupt when there is a
change in the relationship between ISUMRMS
and ISUMLVL.
Set this bit to enable an interrupt when the
waveform buffer is full with resampled data,
which is selected when WF_CAP_SEL = 0 in the
WFB_CFG register.
Set this bit to enable an interrupt when one of
the events configured in WFB_TRIG_CFG occurs.
Set this bit to enable an interrupt when the THD
and power factor measurements are updated,
every 1.024 sec.
Set this bit to enable an interrupt when the
10 cycle rms/12 cycle rms values are updated.
Set this bit to enable an interrupt when the fast
RMS½ values are updated.
Set this bit to enable an interrupt when the
power values in the xWATT_ACC, xVA_ACC,
xVAR_ACC, xFWATT_ACC, xFVA_ACC, and
xFVAR_ACC registers update, after PWR_TIME
8 kSPS samples.
UG-1098
Reset Access
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W
0x0 R/W